NAND Memory Read-Voltage Feedback for Accurate Valley Detection
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Solution Overview
Problem
NAND memory devices experience data accuracy issues due to charge fluctuations over time and temperature variations, affecting the reliability of read operations.
Innovation Solution
A memory device and system that adjusts read voltages based on the number of flipped bits to determine a valley voltage for accurate data reading, using a peripheral circuit or memory controller to iteratively adjust read voltages until a stable valley voltage is achieved, and performs error correction if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed repeatedly on NAND memory cells, then data access speed is maintained, but charge stored in memory cells changes due to use time and temperature variations, affecting reading accuracy
Solution Approach 1:
The patent implements a feedback mechanism by counting the number of flipped bits during read operations and using this information to dynamically adjust the read voltage. The peripheral circuit monitors reading accuracy through bit flip detection and adjusts the read voltage accordingly to maintain accurate data retrieval despite charge fluctuations from repeated use and temperature variations.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on the number of flipped bits detected during read operations. By adjusting the read voltage in response to observed bit flips, the system adapts to charge fluctuations in memory cells caused by repeated use and temperature changes, thereby maintaining reading accuracy without sacrificing access speed.
2Measurement precision
If read voltage is adjusted to compensate for charge changes, then reading accuracy is improved, but additional voltage adjustment operations increase time consumption
Solution Approach 1:
The patent performs preliminary action by detecting and counting flipped bits during the read operation itself, rather than requiring separate calibration steps. The bit flip detection is integrated into the normal read process, allowing the system to gather information about charge changes and adjust voltage proactively without significant time penalty.
Solution Approach 2:
The patent merges the voltage adjustment function with the normal read operation by integrating bit flip detection and voltage adjustment logic into the peripheral circuit that already performs read operations. This combination eliminates the need for separate voltage calibration steps, reducing time consumption while maintaining reading accuracy.
3Measurement precision
If the number of flipped bits is counted to determine valley voltage, then optimal read voltage is identified, but multiple read operations at different voltages increase complexity
Solution Approach 1:
The patent implements self-service by enabling the peripheral circuit to automatically detect flipped bits, determine the number of flips, and adjust the read voltage without external intervention. The system serves itself by using its own read operations to gather information about charge changes and autonomously optimizing the read voltage to identify valley voltage.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a flip bit counter within the peripheral circuit that mediates between the read operation and voltage adjustment. This counter translates raw read data into actionable information about charge changes, enabling the system to identify valley voltage through a structured process that manages complexity.
Data Source
AI summary
According to one aspect of the present disclosure, a memory device is provided. The memory device may include an array of memory cells, including a plurality of memory cells. A preset number of memory cells form a code word. The memory device may include peripheral circuit coupled to the array of memory cells. The peripheral circuit may be configured to obtain the first result corresponding to the code word at the target read voltage. The peripheral circuit may be configured to adjust the target read voltage in accordance with the first result corresponding to the code words at the target read voltage. The peripheral circuit may be configured to obtain the first result corresponding to the code words at the adjusted read voltage. The peripheral circuit may be configured to determine a valley voltage in accordance with a plurality of the first results.