NAND Flash Read Voltage Calibration for LDPC Error Correction

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Solution Overview

Problem

The increasing Bit Error Rate (RBER) in NAND flash memories due to the reduction in process size and increase in stacked layers of 3D NAND flash memory, which the BCH code cannot effectively address, necessitates a more accurate detection voltage for improved error correction capabilities in LDPC decoding.

Innovation Solution

An optimal detection voltage is calculated by performing read operations at multiple voltages, obtaining difference values, and using tangent approximations to determine a weighted optimal voltage for hard decision decoding, followed by soft decision decoding to enhance error correction performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If BCH code is used for error correction, then the device complexity is lower, but the error correction capability is insufficient for modern NAND flash memories with increased RBER

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the decoding parameters by transitioning from BCH code to LDPC code, which provides superior error correction capability for modern NAND flash memories with higher RBER. This parameter change enables the system to handle increased bit error rates resulting from process reduction and increased stacked layers.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements dynamic decoding by combining hard decision decoding (faster) and soft decision decoding (more accurate) in a hybrid approach. The system dynamically selects the appropriate decoding method based on the specific data conditions, optimizing both speed and accuracy for LDPC code processing.

Inventive Principle:
Principle #15Dynamics

2Reliability

If soft decision decoding is used for LDPC, then the error correction capability is improved, but the decoding speed decreases compared to hard decision decoding

Engineering Contradiction:
Improvedecoding capabilityVSAvoiddecoding speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements dynamic decoding by combining hard decision decoding (faster) and soft decision decoding (more accurate) in a hybrid approach. The system dynamically selects the appropriate decoding method based on the specific data conditions, optimizing both speed and accuracy for LDPC code processing.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the decoding process into two distinct phases: hard decision decoding for initial error correction and soft decision decoding for residual errors. This segmentation allows the system to leverage the speed advantage of hard decision while maintaining the accuracy benefit of soft decision, resolving the speed-capability tradeoff.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the detection voltage is not optimized, then the reading operation is simpler, but the bit error rate increases due to inaccurate threshold voltage detection

Engineering Contradiction:
Improvebit error rateVSAvoidvoltage calibration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by pre-calibrating the detection voltage before the actual reading operation. The calibration process determines the optimal detection voltage (Vopt) in advance, ensuring accurate threshold voltage detection during subsequent read operations and minimizing bit error rates without adding complexity to the main reading process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the calibration results to adjust and optimize the detection voltage. The system measures the actual threshold voltage distribution and uses this feedback information to fine-tune the detection voltage, creating a closed-loop system that continuously optimizes reading accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11557353B2Optimal detection voltage obtaining method, reading control method and apparatus of memory
Publication Date: 2023.01.17 MAXIO TECHNOLOGY (HANGZHOU) CO LTD
  • US11557353B2 patent drawing
  • US11557353B2 patent drawing
  • US11557353B2 patent drawing

AI summary

An optimal detection voltage obtaining method, a reading control method and an apparatus are provided. The method includes: obtain a plurality of first difference values and a plurality of second difference values, the second difference value characterizes a difference value of two detection voltages which are adjacent in numerical value, the first difference value characterizes a difference between numbers of memory cells whose threshold voltages respectively equal to the two detection voltages used by the second difference value; dividing the first difference by the second difference to obtain a plurality of tangent approximations; selecting a first tangent approximation and a second tangent approximation from the plurality of tangent approximations, the first tangent approximation is a positive number and the second tangent approximation is a negative number; calculating an optimal detection voltage according to the first tangent approximation, the second tangent approximation, a first detection voltage and a second detection voltage.