NAND Read Voltage Selection Using LDPC Codeword Error Rate
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Solution Overview
Problem
Conventional NAND storage subsystem read voltage determination systems are sub-optimal for Low-Density Parity Check (LDPC) Error Correction Code (ECC) systems, leading to higher average codeword error rates compared to traditional Bose, Chaudhuri, and Hocquenghem (BCH) ECC systems.
Innovation Solution
A storage subsystem read voltage determination system that reads data from multiple read voltage sets, generates bit error probability distributions, and uses error correction capability graphs to identify a read voltage set with a minimum average codeword error rate, optimizing read voltages for NAND storage systems with LDPC ECC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read voltage determination methods are used for NAND storage subsystems, then the average number of bit errors per codeword is minimized, but the average codeword error rate remains sub-optimal for LDPC ECC systems
Solution Approach 1:
The patent changes the optimization parameter from minimizing average bit errors per codeword to minimizing average codeword error rate. This parameter change is achieved by generating error probability distributions for different read voltage sets, constructing error correction capability graphs for the specific ECC type (BCH or LDPC), and determining average codeword error rates based on both the error probability distributions and the error correction capability graphs. This resolves the contradiction by adapting the optimization criterion to match the specific characteristics of the ECC system being used.
Solution Approach 2:
The patent performs preliminary characterization of the error correction capability graph for the specific ECC type before determining optimal read voltages. This preliminary action involves generating the error correction capability graph that captures the relationship between bit error counts and codeword error probability for the specific ECC scheme. By having this graph pre-established, the system can then efficiently determine optimal read voltages by comparing error probability distributions against this known capability model, rather than using a generic minimization approach.
2Reliability
If read voltages are optimized for BCH ECC systems, then bit error minimization is achieved, but data reliability deteriorates for LDPC ECC systems
Solution Approach 1:
The patent applies local quality by tailoring the read voltage determination process to the specific ECC type being used in the storage subsystem. Instead of using a universal bit error minimization approach, the system generates error correction capability graphs specific to either BCH or LDPC ECC, and uses these customized graphs to determine optimal read voltages for each ECC type. This localized approach ensures that the read voltage optimization is adapted to the specific error correction characteristics of the ECC system, thereby improving data reliability for each specific ECC type while maintaining versatility across different ECC implementations.
Solution Approach 2:
The patent changes the optimization parameter from generic bit error minimization to ECC-specific average codeword error rate minimization. By generating error correction capability graphs that are specific to the ECC type (BCH or LDPC) and using these graphs to determine average codeword error rates, the system adapts its optimization criterion to match the specific characteristics of each ECC system. This parameter change enables the system to achieve optimal reliability for each ECC type while maintaining adaptability across different ECC implementations.
Data Source
AI summary
A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.