3D NAND Read Voltage Mapping for Cross-Die Service Uniformity
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Solution Overview
Problem
The increasing differences among memory dies and film layers within memory devices, particularly in 3D NAND structures, affect the quality of service and performance of system products, especially in reliability scenarios like durability and retention.
Innovation Solution
A memory system and method that involves selecting super blocks with matching state parameters, determining and adjusting read voltages based on a mapping table, and updating the table with equilibrium read voltages to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are integrated into a memory device with multiple memory blocks, then storage capacity is increased, but differences among memory dies and film layers cause variations in read voltage requirements affecting service quality and performance
Solution Approach 1:
The patent applies local quality by determining separate read voltages for different super blocks based on their specific state parameters (erase count, retention time). Instead of using a uniform read voltage for all memory blocks, the system tailors the read voltage to the local conditions of each super block, thereby compensating for variations among memory dies and film layers while maintaining high storage capacity
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on the state parameters of super blocks. The memory controller adjusts read voltages according to erase counts and retention times, transforming a static voltage approach into a dynamic one that adapts to the aging and wear characteristics of different memory regions, thus maintaining reliable operation across all stored data
2Reliability
If separate read voltages are determined for each memory block to address variations, then service quality uniformity is improved, but system complexity increases due to multiple voltage management operations
Solution Approach 1:
The patent merges the management of read voltages by grouping memory blocks into super blocks that share common read voltage characteristics. Instead of independently managing voltages for each memory block, the system combines multiple blocks into super blocks and determines a single read voltage for each super block based on its state parameters, thereby reducing the number of voltage management operations while maintaining service quality uniformity
Solution Approach 2:
The patent creates a universal read voltage determination mechanism that serves multiple super blocks simultaneously. The memory controller uses a standardized process to determine read voltages for all super blocks, applying the same methodology across different memory dies and super block configurations, which simplifies the overall system while achieving uniform service quality across diverse memory regions
Data Source
AI summary
An example memory system includes: a memory device and a memory controller. The memory device includes L memory dies, and memory blocks in different memory dies form a super block. The memory controller is configured to: determine first super blocks among super blocks, and the state parameters of first super blocks match the preset state parameters; determine M first read voltages based on first super blocks and first mapping tables; adjust the M first read voltages corresponding to the memory blocks of each first super block to M second read voltages; determine M first equilibrium read voltages based on the equilibrium values of second read voltages corresponding to memory blocks located in the same memory die in first super blocks; and update the first mapping table based on M first equilibrium voltage readings.