3D NAND Read Voltage Sequencing for Back-Pattern Interference
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Solution Overview
Problem
Existing memory devices face challenges in reducing read interference and improving reliability due to the widening of threshold voltage distribution and decreased read windows caused by the back-pattern effect during read operations in three-dimensional NAND memory systems.
Innovation Solution
A novel voltage application approach is implemented in the memory device, involving a series of voltage adjustments on adjacent word lines and the target word line, including pre-pass and read phases with specific voltage transitions to minimize read interference and enhance data sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional read operation is performed on three-dimensional NAND memory, then data can be read from the memory cell, but read interference increases and reliability decreases due to threshold voltage distribution widening
Solution Approach 1:
The read operation is divided into multiple phases (pre-pass phase, first read phase, second read phase) with different voltage levels applied to adjacent word lines. This segmentation allows the system to gradually increase read interference rather than applying maximum interference all at once, thereby reducing the harmful back-pattern effect while maintaining reliable data reading.
Solution Approach 2:
The patent dynamically adjusts the voltage levels applied to adjacent word lines during different phases of the read operation. In the pre-pass phase, a first pass voltage is applied; in the first read phase, a second pass voltage (lower than the first) is applied; and in the second read phase, a third pass voltage (lower than the second) is applied. This dynamic voltage adjustment reduces read interference over time while maintaining sufficient read accuracy.
2Measurement precision
If high pass voltage is applied to adjacent word lines during read operation, then data sensing can be performed, but threshold voltage distribution widens due to back-pattern effect
Solution Approach 1:
The patent applies different pass voltages to adjacent word lines during different phases of the read operation. The voltage levels are dynamically reduced across phases (first pass voltage > second pass voltage > third pass voltage), which allows the system to maintain data sensing accuracy while minimizing the back-pattern effect that causes threshold voltage distribution widening.
Solution Approach 2:
The read operation uses periodic voltage applications across multiple phases with decreasing voltage levels. This periodic action pattern allows the system to perform necessary data sensing while gradually reducing the impact on threshold voltage distribution, thereby maintaining stability in the memory cell characteristics.
3Productivity
If pass voltage is applied to adjacent word lines, then read operation can proceed, but read window decreases due to back-pattern effect
Solution Approach 1:
The read operation is segmented into multiple phases with progressively lower pass voltages applied to adjacent word lines. This segmentation allows the system to maintain read operation efficiency while reducing the back-pattern effect that causes read window narrowing, thereby improving reliability.
Solution Approach 2:
The patent changes the voltage parameter applied to adjacent word lines across different phases of the read operation. By sequentially reducing the pass voltage (first pass voltage > second pass voltage > third pass voltage), the system maintains sufficient read efficiency while minimizing the harmful back-pattern effect that would otherwise narrow the read window.
Data Source
AI summary
The present disclosure provides a memory device and an operating method, and a memory system thereof, the memory device includes a memory array, a peripheral circuit coupled to the memory array, a target word line coupled to memory cells in the memory array, and a first word line adjacent to the target word line; the peripheral circuit is configured to: in a pre-pass phase for performing a read operation on a memory cell coupled to the target word line, apply a first pass voltage to the first word line; in a first sub-phase of a first read phase after the pre-pass phase, reduce the voltage on the first word line from the first pass voltage to a first voltage; in a second sub-phase of the first read phase, increase the voltage on the first word line from the first voltage to a second pass voltage.