NAND Memory Read Voltage Staging for Retention Error Reduction
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Solution Overview
Problem
The accuracy of data reading in NAND memory devices deteriorates over time due to charge retention issues, leading to increased read errors that conventional error correction methods struggle to address efficiently.
Innovation Solution
Implementing a memory device with multiple stages of read voltages, where the second stage has a lower read voltage than the first stage, utilizing a target valley voltage and a predicted valley voltage to optimize read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used to address read errors, then read errors can be corrected, but the response time increases and reading accuracy deteriorates over time due to charge retention issues
Solution Approach 1:
The patent applies preliminary action by performing a first read operation at a first read voltage before the final read operation. This initial read at a higher voltage helps to refresh the charge in the memory cell and provides preliminary data that can be used to determine the final read result, thereby reducing the need for repeated read retries and improving overall response time while maintaining high reading accuracy
Solution Approach 2:
The patent implements periodic action by using multiple staged read operations with different voltages. The first read operation at a higher voltage is followed by a second read operation at a lower voltage, creating a periodic reading sequence that optimizes both speed and accuracy. This multi-stage approach allows the system to quickly assess data integrity and then perform precise reading only when necessary
2Measurement precision
If multiple read operations are performed to improve reading accuracy, then reading accuracy improves, but the response time increases
Solution Approach 1:
The patent applies partial action by performing a first read operation that may not be sufficient for final data retrieval but serves to refresh the charge and provide preliminary information. This partial read action prepares the memory cell for a more accurate second read operation, reducing the need for additional read attempts and optimizing the balance between precision and response time
Data Source
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AI summary
Examples of the present application disclose a memory device, a memory system, a memory controller and an operating method, the memory device includes: a memory cell array including memory cells with multiple storage bits, a preset number of the memory cells form one code word, and the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage corresponding to the second stage is less than the read voltage in the first stage; a peripheral circuit coupled to the array of memory cells and configured to: obtain the target valley voltage in the first target stage, the first target stage including at least one first stage among multiple first stages corresponding to multiple pages; take the target valley voltage as a read voltage at which a read operation is performed on the at least one code word; and obtain the predicted valley voltage in the second target stage in accordance with the target valley voltage in the first target stage, the second target stage including the remaining first stage and/or second stage, the read voltage of the second target is less than the read voltage of the first target.