3D NAND Memory Signal Routing Through Interlayer Gaps
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Solution Overview
Problem
The increasing demand for smaller semiconductor dies with enhanced functionality leads to signal line congestion, making it impossible to include all necessary signal lines within the same die without increasing its size.
Innovation Solution
Incorporating metal interlayer segments between memory structures on the semiconductor die to communicate signals from above the memory structures to below, allowing for efficient routing and reducing congestion without increasing the die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more signal lines are routed within a semiconductor die, then functionality is enhanced, but signal line congestion occurs
Solution Approach 1:
The patent introduces through-silicon vias (TSVs) to route signals vertically through the substrate, transitioning from planar 2D routing to 3D routing. This dimensional change allows signal lines to pass through the substrate thickness, effectively adding a vertical dimension to signal routing and reducing horizontal congestion on the die surface.
Solution Approach 2:
The patent segments the substrate into multiple levels or layers by creating through-holes and filling them with conductive material. This segmentation allows different signal lines to be routed at different vertical levels, separating conflicting signal paths and reducing congestion in the horizontal plane.
2Area of moving object
If the semiconductor die size is reduced, then device size is minimized, but signal line routing becomes congested
Solution Approach 1:
By utilizing the substrate thickness dimension through TSVs, the patent enables signal routing in the vertical direction. This allows the horizontal die area to be minimized while maintaining adequate signal routing capacity through the third dimension, effectively decoupling die size from routing complexity.
Solution Approach 2:
The patent embeds conductive structures within the substrate by creating through-holes and filling them with conductive material. This nesting approach places signal routing pathways inside the substrate volume rather than only on the surface, enabling compact die design with sufficient routing capacity.
Data Source
AI summary
An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.