3D NAND Charge Trap Layer Segmentation for Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3-D nonvolatile memory devices face data loss due to charge leakage between memory cells, and the use of stoichiometric nitride charge trap layers results in slow erase operations.
Innovation Solution
The semiconductor device incorporates alternately stacked word lines and interlayer insulating layers with a channel layer penetrating through, surrounded by first charge trap layers doped with impurities, and second charge trap layers without impurities, which are arranged to prevent charge leakage and improve erase speed while maintaining data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the charge trap layer is made of Si-rich nitride to improve erase speed, then erase operation speed increases, but stored data is lost because electric charges move between memory cells
Solution Approach 1:
The charge trap layer is divided into multiple discrete charge trap layers, each surrounded by charge blocking layers. This segmentation prevents charge migration between memory cells while maintaining the beneficial properties of Si-rich nitride for fast erase operations in each individual charge trap layer.
Solution Approach 2:
Charge blocking layers are introduced as intermediary structures between adjacent charge trap layers. These blocking layers act as barriers that prevent electric charges from moving between memory cells, thereby preserving data retention while allowing fast erase operations within each charge trap layer.
2Reliability
If the charge trap layer is made of stoichiometric nitride to prevent data loss, then data retention is maintained, but erase operation speed becomes slow
Solution Approach 1:
Different regions of the memory device have different charge trap layer compositions optimized for their specific functions. Individual charge trap layers can use Si-rich nitride for fast erase operations, while charge blocking layers use stoichiometric nitride to prevent charge migration, achieving both fast erase and data retention locally.
Solution Approach 2:
The memory device employs a composite structure combining Si-rich nitride charge trap layers (for fast erase) with stoichiometric nitride charge blocking layers (for data retention). This composite approach integrates the advantages of both material types to simultaneously achieve high erase speed and reliable data storage.
3Productivity
If charge trap layers are coupled in conventional 3-D structure to increase integration density, then vertical stacking is achieved, but charge leakage occurs between stacked memory cells
Solution Approach 1:
Charge blocking layers are positioned between adjacent charge trap layers in the vertical stack, acting as intermediary barriers that prevent charge leakage while maintaining the high integration density of the 3-D vertically stacked memory cell structure.
Solution Approach 2:
The continuously coupled charge trap layer structure is segmented into discrete, isolated charge trap layers separated by charge blocking layers. This segmentation maintains vertical stacking for high integration while preventing harmful charge migration between memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances erase characteristics and data retention by preventing charge movement between memory cells, achieving improved erase speed and maintaining data integrity.
Implementation Method 1
first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities
Data Source
AI summary
A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.