NAND Flash Memory Leakage Current Reduction via Segmented Selection Gates

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Solution Overview

Problem

NAND flash memory devices experience significant leakage current due to boosted channel voltages, which can lead to unintended programming of non-selected cells and degradation of punch-through characteristics, particularly as line widths decrease with high integration trends.

Innovation Solution

The implementation of a NAND flash memory device structure that includes device isolation layers, specific impurity diffusion layers, and strategically arranged selection gate lines to minimize leakage current, with programming methods that manage channel voltages to prevent punch-through and DIBL phenomena.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high integration trends are pursued with decreased line widths, then integration density is improved, but leakage current increases and punch-through characteristics degrade

Engineering Contradiction:

Improveintegration densityVSAvoidleakage current

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The selection gate line is divided into a first selection gate line and a second selection gate line that are arranged in series. This segmentation allows the gate control to be distributed across multiple stages, improving the ability to control channel voltage and reduce leakage current while maintaining high integration density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical stacking dimension by arranging the first and second selection gate lines in series along the channel length direction. This dimensional approach allows for better voltage distribution and control without increasing the planar footprint, thus maintaining high integration density while reducing leakage.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If high integration trends are pursued with decreased line widths, then integration density is improved, but punch-through characteristics degrade

Engineering Contradiction:

Improveintegration densityVSAvoidpunch-through characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

By segmenting the selection gate into two series-connected gate lines, the patent achieves better control over the channel potential distribution. This segmentation prevents excessive voltage buildup that could cause punch-through, while allowing continued scaling for high integration density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first selection gate line acts as an intermediary between the control gate and the second selection gate line. It mediates the voltage distribution along the channel, preventing direct punch-through by distributing the electric field more evenly across the channel length.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If boosted channel voltages are applied for programming, then programming speed is improved, but leakage current increases

Engineering Contradiction:

Improveprogramming speedVSAvoidleakage current

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent employs dynamic voltage control through the series-connected selection gate lines, where voltages can be adjusted independently on the first and second gates. This dynamic control allows optimized programming voltages to be applied while maintaining low leakage current through proper voltage distribution.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameters applied to the first and second selection gate lines independently. By adjusting these voltage parameters, the system can achieve fast programming when needed while minimizing leakage current through optimized voltage distribution across the series-connected gates.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leakage current and maintains the integrity of programming operations, enhancing the reliability and integration density of NAND flash memory devices.

Implementation Method 1

degradation of punch-through characteristics

Methodology Applied

Scientific EffectPunch-through:

Implementation Method 2

prevent punch-through and DIBL phenomena

Methodology Applied

Scientific EffectDIBL (Drain Induced Barrier Lowering):

Data Source

PatentUS7477548B2NAND flash memory device and methods of its formation and operation

Publication Date: 2009.01.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A NAND flash memory device, and methods of forming and operating the same are provided. The NAND flash memory device includes first and second selection gate lines sequentially disposed at one side of a plurality of cell gate lines. A first selection transistor including the first selection gate line serves as a buffer for decreasing a highly boosted channel voltage of a non-selected cell to minimize the leakage current of the NAND flash memory device.