3D NAND Select Cut Structure for Channel Hole Formation
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing data storage capacity and electrical characteristics, particularly in efficiently arranging memory cells to optimize storage and performance.
Innovation Solution
The semiconductor device incorporates a gate stack structure with a staircase design, including a cut structure that has a narrow section and a wide section, where the narrow section is adjacent to the memory channel and the wide section is adjacent to the dummy channel and support structures, allowing for improved electrical characteristics and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used, then the manufacturing process is simpler, but the electrical characteristics are inferior
Solution Approach 1:
The gate structure is segmented into multiple distinct components: gate electrode, gate insulating film, interlayer insulating film, and cap insulating film. Each layer serves a specific function, with the cap insulating film providing additional electrical isolation and the interlayer insulating film enabling proper spacing for bit line formation. This segmentation allows optimization of electrical characteristics while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Quantity of substance
If memory channel holes are formed with standard dimensions, then the formation process is easier, but the storage capacity is limited
Solution Approach 1:
The memory channel holes extend in the vertical dimension through multiple insulating film layers, increasing the effective storage volume without proportionally increasing the planar footprint. The holes penetrate through the gate insulating film, interlayer insulating film, and cap insulating film, creating three-dimensional storage structures that enhance capacity while using conventional hole formation techniques adapted for increased depth.
3Reliability
If the cut structure has uniform width, then the manufacturing is simpler, but the electrical characteristics and storage capacity are suboptimal
Solution Approach 1:
The cut structure exhibits varying widths at different locations: a first width in the gate insulating film region and a second width in the interlayer insulating film region. This local variation optimizes electrical characteristics by providing appropriate spacing in different vertical zones, with the narrower section enabling better field control and the wider section facilitating bit line formation. The stepped configuration is achieved through selective etching processes that modify the cut structure at specific depth ranges.
4Volume of moving object
If the gate insulating film is thin, then the device size is reduced, but the formation of memory channel holes becomes more difficult
Solution Approach 1:
The gate insulating film is formed to a predetermined thin thickness before memory channel hole formation begins. This preliminary sizing allows subsequent hole formation processes to target precise depths, ensuring holes extend through the thin gate insulating film and into underlying structures without excessive over-etching. The predetermined thickness serves as a reference for controlling hole depth and maintaining proper spacing between adjacent memory channels.
Data Source
AI summary
A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure on the source structure, the gate stack structure including a word line, a gate upper line and a staircase structure, a memory channel structure and a dummy channel structure extending through the gate stack structure, a cut structure extending through the gate upper line, and a bit line overlapping with the memory channel structure. The cut structure includes a narrow section, and a wide section nearer to the staircase structure than the narrow section. A width of the narrow section is less than a width of the wide section.