3D NAND Select Gate Bias Gradation for Neighbor Interference
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Solution Overview
Problem
In three-dimensional NAND memory structures, neighboring select gates in sub-divisions of NAND blocks experience interference during programming operations due to etching processes, leading to disturbances in memory cell operations.
Innovation Solution
A biasing scheme is introduced for the GIDL select gates, where the upper drain side select gate layer is biased to a first voltage for selected sub-divisions and the lower layer is biased to a second voltage for un-selected sub-divisions, reducing interference by optimizing the bias levels for each layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching processes are used to create sub-divisions in NAND blocks, then manufacturing precision is improved, but neighbor select gate interference increases
Solution Approach 1:
The patent applies local quality by assigning different bias voltages to different select gate layers based on their specific operational needs. The first drain side select gate layer receives a first bias voltage while the second drain side select gate layer receives a second bias voltage, allowing each layer to be optimized independently for its local function, thereby reducing interference between neighboring sub-divisions while maintaining manufacturing precision
Solution Approach 2:
The patent changes the electrical parameter (bias voltage) of the select gate layers to resolve the interference issue. By adjusting the bias voltage levels for different select gate layers, the patent optimizes the electrical characteristics to minimize neighbor select gate interference while preserving the etched sub-division structure
2Device complexity
If uniform bias is applied to all select gates, then device complexity is reduced, but programming efficiency decreases due to interference
Solution Approach 1:
The patent segments the bias control system by dividing the select gate layers into distinct groups (first drain side select gate layer and second drain side select gate layer) that receive different bias voltages. This segmentation allows independent optimization of each layer's bias level, reducing interference effects and improving programming efficiency without excessive complexity increase
Solution Approach 2:
The patent introduces dynamic bias control where different bias voltages are applied to different select gate layers based on operational requirements. This dynamic approach allows the system to adapt bias levels to minimize interference during programming operations, thereby improving programming efficiency while maintaining manageable device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes neighbor select gate interference, enhancing the programming efficiency and reliability of three-dimensional NAND memory by optimizing the bias levels for individual select gate layers.
Implementation Method 1
one or more additional select gates can be added between the drain side select gates and the bits lines for use in erase through a gate induced drain leakage (GIDL) mechanism
Data Source
AI summary
To address neighbor select gate interference between neighboring NAND block sub-divisions when one sub-division is program selected and its neighbor is un-selected, a biasing scheme for the GIDL select gates is introduced to reduce such disturbs. In a three-dimensional NAND memory with a sub-division structure and with two drain side GIDL select gate layers, when a sub-division is program selected and its neighboring sub-division is un-selected, the upper of the two drain side GIDL select gate layers is biased to a first voltage for all of the sub-divisions, while for the lower drain side GIDL select gate layer the gates are biased to be off for the un-selected sub-divisions and biased at a second voltage for the selected sub-division, where the second voltage is configured to turn on the lower drain side GIDL select gates and the first voltage is of a higher level than the second voltage.