NAND Select Gate Parasitic Coupling Control
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Solution Overview
Problem
NAND flash memory devices face non-uniform erase threshold voltages due to parasitic coupling effects, which affect the performance and scaling of the memory array as the device size increases.
Innovation Solution
The solution involves modifying the select gates in the NAND memory array by switchably coupling or isolating the control gate and floating gate, allowing the select gates to behave like memory cell transistors during erase operations, thereby reducing parasitic noise and ensuring uniform erase voltages across the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If select gates are used in NAND flash memory devices, then the memory array can be accessed and operated, but non-uniform erase threshold voltages occur due to parasitic coupling effects
Solution Approach 1:
The patent applies the dynamics principle by making the select gate structure configurable between two states: connected (control gate coupled to floating gate) and disconnected (control gate isolated from floating gate). This dynamic reconfiguration allows the select gate to adapt its behavior based on the operational phase, thereby resolving the contradiction between enabling memory array access and maintaining erase threshold voltage uniformity.
Solution Approach 2:
The patent implements parameter changes by modifying the electrical coupling state between the control gate and floating gate of the select gate. During erase operations, the coupling is changed from connected to disconnected, which alters the electrical parameters of the select gate to minimize parasitic coupling effects. This parameter change enables uniform erase threshold voltages across all memory cells while preserving the select gate's functionality during other operations.
2Quantity of substance
If device size increases to improve memory capacity, then storage capability improves, but parasitic coupling effects worsen and affect performance
Solution Approach 1:
The patent applies the local quality principle by implementing a selective configuration approach where only the select gates adjacent to edge wordlines are modified with the disconnectable coupling structure. This localized modification targets the specific area where parasitic coupling effects are most problematic, allowing the majority of the memory array to maintain its standard structure while improving overall performance as device size scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that all memory cells experience the same parasitic noise and coupling effects, leading to improved uniformity in erase voltages and enhanced performance and scalability of the NAND flash memory device.
Implementation Method 1
The capacitance of the select gates, which are driven to a high voltage as a result of the erase operation, affects the edge wordlines, which experience a different parasitic coupling effect, such as parasitic noise, from the adjacent select gates
Data Source
AI summary
Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.