NAND Flash Select Gate Dielectric Formation
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Solution Overview
Problem
The existing manufacturing processes for NAND flash memory chips face challenges in forming memory cells and peripheral circuits efficiently, as they require different device structures, leading to increased costs and defective units due to the need for multiple processing steps.
Innovation Solution
The solution involves forming conductive strips along the sides of select gates to electrically connect the floating gate and control gate layers, allowing for the formation of a unitary gate without etching through the interpoly dielectric layer, and depositing a control gate directly on a new select gate dielectric formed on the substrate, thereby simplifying the process and reducing the risk of damaging the gate dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etching is performed through the IPD layer to form a unitary gate in select transistors, then electrical connection between floating gate and control gate is achieved, but the gate dielectric may be damaged
Solution Approach 1:
The patent forms select gate dielectric material in the select transistor region before depositing the IPD layer and floating gate material. This preliminary action creates a protective dielectric layer that prevents etching damage to the gate dielectric during subsequent unitary gate formation, while still allowing electrical connection between the floating gate and control gate through controlled etching of the select gate dielectric.
2Adaptability or versatility
If different device structures are used for memory cells and peripheral circuits, then specific functional requirements are met, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies local quality by forming select gate dielectric material specifically in the select transistor region, while leaving the IPD layer intact in memory cell regions. This localized modification allows different device structures for memory cells and peripheral circuits to coexist using the same manufacturing process steps, maintaining functional adaptability without increasing overall manufacturing complexity.
Data Source
AI summary
A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes an opening through an interpoly dielectric layer, floating gate layer, and tunnel dielectric layer, the opening separated from the substrate surface by a select gate dielectric on the substrate surface, the opening filled by a control gate layer.