NAND Select Gate Erase via GIDL While Preserving Stored Data
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Solution Overview
Problem
Non-volatile NAND memory architectures face issues with select gate threshold voltage drift over time, requiring erase and reprogramming, which often necessitates erasing the data content of memory cells, leading to data loss.
Innovation Solution
A technique is introduced to selectively erase the drain side select gates of NAND strings using gate induced drain leakage (GIDL) mechanism, transferring holes to under the select gate for Fowler-Nordheim tunneling, maintaining data integrity by not erasing memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If select gates are erased and reprogrammed to correct threshold voltage drift, then select gate performance is improved, but data content of memory cells is lost
Solution Approach 1:
The patent segments the erase operation to affect only the select gates while preserving memory cells. By applying erase voltages selectively to drain side select gates through specific word line and bit line voltage combinations, the system divides the erase function into targeted portions, refreshing only the select gates that exhibit threshold voltage drift without erasing the data stored in memory cells.
Solution Approach 2:
The patent implements local quality by creating different voltage conditions in different regions of the NAND string. Memory cells are maintained at voltages that preserve their charge state, while select gates receive specific voltage combinations that induce hole generation and erasure. This localized voltage control ensures that erasure effects are confined to select gates while memory cells retain their data.
2Reliability
If block erase is performed to refresh select gates, then select gate reliability is improved, but productivity decreases due to loss of stored data requiring reprogramming
Solution Approach 1:
The patent divides the memory structure into functionally distinct regions with different voltage requirements during the refresh operation. By segmenting the voltage application strategy, select gates undergo erasure while memory cells remain in a read-retain mode, avoiding the need to erase and reprogram entire blocks and thereby maintaining productivity.
Solution Approach 2:
The patent applies preliminary voltage setup to memory cells before the erase operation on select gates. By pre-establishing voltage conditions on word lines and bit lines that protect memory cell charge, the system prepares the memory structure to withstand the erase process without losing data, thus maintaining productivity while refreshing select gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for refresh of select gates while preserving data content, enabling data encryption and secure data retention.
Implementation Method 1
A technique is introduced to selectively erase the drain side select gates of NAND strings using gate induced drain leakage (GIDL) mechanism
Implementation Method 2
transferring holes to under the select gate for Fowler-Nordheim tunneling
Data Source
AI summary
To allow for the erase of the drain side select gates of NAND strings while maintaining the data content of the memory cells, while erase inhibiting the memory cells of a NAND string, holes are generated in the drain region through the gate induced drain leakage (GIDL) mechanism and transferred to under the select gate, where they are then used to erase the select gate by Fowler-Nordheim mechanism. This allows for the refresh of the drain side select gates while retaining the data content of the NAND strings. This approach can also be used for data encryption, since, by erasing the drain side select gates, a block of data can be rendered unreadable; but, since the data content is not erased, it can later be recovered.