NAND Flash Select Gate Scanning After Erase for Detection Accuracy
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Solution Overview
Problem
Existing select gate scan schemes in non-volatile memory devices, particularly NAND flash memory, suffer from inaccuracies due to variability in NAND chain resistance, leading to premature retirement of functional blocks or continued use of defective blocks, compromising device reliability and performance, especially in data center environments.
Innovation Solution
Implementing a tag-wait-erase-scan select gate scan scheme that delays select gate scan operations until an erase operation is performed on blocks that satisfy a scan triggering condition, ensuring scans are conducted on erased blocks to enhance accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If select gate scan operations are performed on programmed blocks, then scan operations can be executed more frequently, but measurement precision deteriorates due to variability in NAND chain resistance
Solution Approach 1:
The patent applies preliminary action by performing an erase operation on the block before conducting the select gate scan operation. This preparatory step ensures that the block is in a known initial state (erased state) with minimal NAND chain resistance variability, thereby improving measurement precision. The erase operation is executed in advance of the scan operation, creating optimal conditions for accurate threshold voltage detection without compromising scan operation frequency.
2Device complexity
If select gate scan operations are performed on programmed blocks, then device complexity is reduced, but reliability deteriorates due to premature retirement or continued use of defective blocks
Solution Approach 1:
The patent employs preliminary action by erasing the block before scanning, which improves reliability by ensuring accurate detection of select gate threshold voltage degradation. The erase operation prepares the block in a standardized state, enabling more reliable identification of defective blocks versus functional blocks that should be retained. This prevents both premature retirement of functional blocks and continued use of defective blocks.
Solution Approach 2:
The patent changes the state parameter of the block from programmed to erased before performing the scan operation. This parameter change (erase state) reduces NAND chain resistance variability and provides a consistent baseline for threshold voltage measurements, thereby improving the reliability of block retirement decisions without significantly increasing device complexity.
3Measurement precision
If select gate scan operations are delayed until erase operation, then measurement precision improves, but loss of time increases
Solution Approach 1:
The patent merges the erase operation and scan operation into a coordinated sequence where the erase operation serves dual purposes: it prepares the block for accurate scanning while also being a necessary maintenance operation. By combining these operations and triggering the scan after erase, the patent minimizes the effective time loss since the erase operation would have been performed anyway for memory management purposes.
Solution Approach 2:
The system uses the erase operation itself to prepare the block for scanning, making the erase operation self-serving for both its primary purpose (memory management) and the secondary purpose of enabling accurate scan measurements. This self-service approach reduces the need for separate preparatory steps, thereby minimizing the time penalty associated with improved measurement precision.
Data Source
AI summary
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including determining that a scan triggering condition has been satisfied for a block of the memory device. The operations further include setting a scan flag associated with the block to a first value indicative of satisfaction of the scan triggering condition. The operations further include delaying a scan operation of the block until an erase operation is performed on the block. The operations further include, responsive to performing the erase operation on the block, performing the scan operation on the block. The operations further include setting the scan flag associated with the block to a second value.