3D NAND Bottom Select Gate Layout for Faster Programming
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Solution Overview
Problem
The increasing density of memory cells in 3D NAND flash memory leads to longer programming times due to limited driving capability of the array voltage, exacerbated by the reduction in peripheral circuit area and parasitic RC effects, which affect signal transmission and response.
Innovation Solution
Implementing a memory device with a bottom select gate layer that includes bottom select gates connected to the same select line, where different bottom select gates are programmed to different threshold voltages, and applying distinct voltages to these select lines to achieve selective turn-on and turn-off, thereby reducing the parasitic RC effect and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased in 3D NAND, then the storage capacity is improved, but the programming time is extended due to limited driving capability of array voltage
Solution Approach 1:
The bottom select gate layer is divided into multiple independent bottom select gate lines (first bottom select gate line, second bottom select gate line, third bottom select gate line), each capable of being independently controlled with different voltages. This segmentation allows selective activation of specific memory strings, improving programming efficiency by reducing the time required to program high-density memory cells.
2Area of stationary object
If the peripheral circuit area is reduced to allow further scaling, then the device size is improved, but the driving capability of array voltage is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture with multiple bottom select gate lines arranged vertically. This dimensional change allows for increased functionality and driving capability without proportionally increasing the peripheral circuit area, as the additional control lines are integrated in the vertical dimension rather than consuming lateral space.
3Device complexity
If multiple memory strings are controlled by the same select line, then the device complexity is reduced, but the parasitic RC effects affect signal transmission and response
Solution Approach 1:
The single select line is segmented into multiple independent bottom select gate lines (first, second, and third bottom select gate lines), each capable of independent voltage control. This segmentation reduces the parasitic RC effects by distributing the control signals across multiple smaller lines rather than using one large line, thereby improving signal transmission quality and response time while maintaining manageable device complexity.
Solution Approach 2:
Different bottom select gate lines are assigned different voltage levels (first voltage, second voltage, third voltage) to create local electrical conditions optimized for specific memory string operations. This local quality approach allows selective turn-on and turn-off of adjacent memory strings, minimizing parasitic RC effects on non-selected strings while maintaining simple overall device structure.
Data Source
AI summary
The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.