NAND Select Gate Voltage Control for Faster Read Transitions
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Solution Overview
Problem
In semiconductor memory devices like NAND flash memory, the transition to target voltages during read operations is slow due to resistance imbalances between outer and inner select gate lines, leading to inefficiencies and potential data disturb issues.
Innovation Solution
A semiconductor memory device is configured to independently control voltages supplied to outer and inner select gate lines using a voltage generation circuit, adjusting resistance values within the driver circuit to ensure uniform voltage application across these lines, thereby accelerating the read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single voltage supply method is used for all select gate lines, then the circuit structure is simple, but the voltage transition speed is slow due to resistance imbalances between outer and inner select gate lines
Solution Approach 1:
The select gate lines are segmented into outer select gate lines and inner select gate lines, with separate voltage supply circuits for each group. This segmentation allows independent optimization of voltage transition speed for each line type, resolving the contradiction between speed and complexity by applying different control strategies to different segments.
Solution Approach 2:
Different voltage control characteristics are applied to different locations: outer select gate lines receive voltage control optimized for their higher resistance, while inner select gate lines receive voltage control optimized for their lower resistance. This local quality approach enables each region to operate at optimal speed without unnecessarily complicating the entire system.
2Reliability
If voltage is supplied to all select gate lines simultaneously, then the read operation can proceed, but resistance imbalances cause non-uniform voltage distribution leading to data disturb issues
Solution Approach 1:
The voltage supply is segmented into separate circuits for outer and inner select gate lines, allowing independent voltage control. This ensures uniform voltage distribution across all lines by compensating for resistance differences, thereby improving data read accuracy without requiring complex global control mechanisms.
Solution Approach 2:
The voltage control parameters (such as voltage levels and timing) are changed differently for outer and inner select gate lines based on their respective resistance characteristics. This parameter optimization ensures reliable voltage distribution and prevents data disturb while maintaining manageable circuit complexity.
3Stability of the object's composition
If the resistance values of select gate lines are made equal, then uniform voltage distribution is achieved, but the physical layout and routing become more difficult
Solution Approach 1:
Instead of forcing all select gate lines to have equal resistance (which would complicate layout), the patent applies local quality by providing different voltage control characteristics to outer and inner lines. This compensates for inherent resistance differences caused by physical layout constraints, achieving uniform voltage distribution without sacrificing manufacturing ease.
Solution Approach 2:
The voltage control parameters are adjusted according to the specific resistance characteristics of outer and inner select gate lines. This allows the physical layout to remain flexible and easy to manufacture while still achieving stable and uniform voltage distribution through parameter optimization.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.