3D NAND Select Transistor Barrier Metal Extraction
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Solution Overview
Problem
In three-dimensional NAND type flash memory devices, achieving optimal ON/OFF properties for select transistors while minimizing leak current and reducing the area of wiring regions for connection to various wiring lines is challenging, as existing technologies struggle to balance selectivity and integration density.
Innovation Solution
A nonvolatile semiconductor memory device with a structure featuring alternately laminated conductive layers and interlayer insulating layers, where conductive layers function as gate electrodes for memory cells and select transistors, and a common contact connects multiple conductive layers without a barrier metal at their boundary, enhancing selectivity and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier metal is formed at the boundary between conductive layers and contacts, then adhesion and corrosion resistance are improved, but contact resistance increases and select transistor performance deteriorates
Solution Approach 1:
The invention extracts the barrier metal from the boundary region between conductive layers and contacts, eliminating it only where it would cause harmful effects. The barrier metal is retained in other regions to maintain adhesion and corrosion resistance, while the boundary region achieves low contact resistance through direct contact between conductive layers and contacts.
Solution Approach 2:
The invention applies different structural configurations to different regions: barrier metal is present in regions where adhesion and corrosion resistance are needed, but absent at the conductive layer-contact boundary where low contact resistance is critical. This local differentiation resolves the contradiction between reliability and harmful factors.
2Reliability
If select transistor size is increased to improve ON/OFF properties, then selection characteristics improve, but wiring region area increases
Solution Approach 1:
The invention transitions from planar transistor design to three-dimensional stacked design, where multiple conductive layers are stacked vertically to form select transistors. This vertical stacking achieves high selection characteristics without increasing the planar wiring region area, effectively resolving the contradiction between performance and area.
Solution Approach 2:
The invention nests multiple conductive layers within each other in a vertical stack, with each layer serving as a gate electrode for memory cells or select transistors. This nested configuration achieves high transistor performance in the vertical dimension while maintaining compact planar footprint.
Data Source
AI summary
The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.