3D NAND Global Selection Line Layout Without Metal Interconnects
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Solution Overview
Problem
Three-dimensional NAND flash memory devices face challenges in integration and fabrication complexity due to the complexity of global selection line structures.
Innovation Solution
The memory device incorporates a substrate with a stack structure featuring alternating insulating and conductive layers, including global selection line structures with unique strip and connection parts that are integrated through a staircase layout, reducing the need for metal interconnects and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional metal interconnect structures are used to connect global selection lines, then wiring complexity increases and fabrication complexity increases
Solution Approach 1:
The patent extracts and eliminates the metal interconnect structures from the global selection line configuration. Instead of using separate metal interconnects to connect global selection lines across memory array areas, the design directly integrates the global selection lines into the stack structure through patterning, removing the unnecessary metal wiring layer and simplifying both the wiring architecture and fabrication process
Solution Approach 2:
The patent merges the global selection line structures with the stack structure by directly patterning the global selection lines within the stack formation process. This integration combines what were previously separate components (global selection lines and stack structure) into a unified structure, eliminating the need for additional metal interconnect layers and reducing overall device complexity
2Device complexity
If global selection line structures are extended across staircase structure area, then integration is improved, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary patterning of the global selection lines during the stack structure formation process itself, before subsequent fabrication steps. By establishing the global selection line patterns early in the fabrication sequence while the stack structure is being formed, the design achieves high integration without requiring additional complex fabrication steps later in the process
Data Source
AI summary
A memory device includes a substrate and a stack structure. A lower portion of the stack structure includes a first global selection line structure and a second global selection line structure. The first global selection line structure includes a first long strip, a first short strip and a first connection part connecting the first long strip and the first short strip. The first long strip and the second strip extend in a first direction, and the first connection part extends in a second direction different from the first direction. The first long strip passes through a staircase structure area from a first memory array area extending continuously to a second memory array area. The second global selection line structure is adjacent to the first global selection line structure and is divided into two portions separated from each other by the first connection part of the first global selection line structure.