NAND Memory Separator Structure Width Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current NAND architecture and fabrication methods face challenges in achieving efficient and compact memory cell configurations due to limitations in separator structure design, which affect the packing density and performance of vertically stacked memory cells.
Innovation Solution
The method involves forming merged openings to create narrower separator structures between memory-block-regions, allowing for tighter packing and improved integration with conventional slits during the removal and replacement of sacrificial material to form conductive wordline levels in NAND memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional separator structures are used between memory-block-regions, then the structure is simpler to manufacture, but the packing density and integration efficiency are reduced
Solution Approach 1:
The separator structure is divided into multiple segments corresponding to different memory-block-regions. Each segment can be independently formed and optimized, allowing for narrower overall separator width while maintaining manufacturability through staged fabrication processes
Solution Approach 2:
The separator structure transitions from a conventional planar configuration to a three-dimensional stacked architecture that integrates with vertically stacked memory cells. This dimensional change enables narrower in-plane separator width while providing additional vertical space for routing and isolation functions
2Area of stationary object
If narrower separator structures are formed, then the packing density of memory cells is improved, but the fabrication process becomes more complex
Solution Approach 1:
The separator structure formation is merged with the formation of insulative levels and conductive wordline levels. By combining multiple functions into a single integrated structure formed through coordinated etching and deposition steps, the process achieves narrow separator width without proportionally increasing fabrication complexity
Solution Approach 2:
Sacrificial material is deposited and patterned in advance to define the precise locations and widths of separator structures before final memory cell formation. This preliminary structuring enables narrow separators to be formed with high precision using standard lithography and etching processes
Data Source
AI summary
Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.