NAND Memory Shield Line Layout for Inter-Chip Noise Isolation
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Solution Overview
Problem
NAND flash memory systems face challenges in suppressing noise propagation between the array chip and the circuit chip, which can affect data storage and retrieval operations, and existing solutions may introduce additional noise or operational instability.
Innovation Solution
The implementation of a shield line between the bonding surface and the memory cell array, which is not electrically coupled to the shield line, helps in reducing noise propagation between the array chip and the circuit chip, and by disconnecting the shield line between the plane and non-plane regions, it prevents noise from spreading across different regions, thereby stabilizing the power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a shield line is electrically coupled to reduce noise propagation, then noise suppression is improved, but noise may propagate to other regions and cause operational instability
Solution Approach 1:
The shield line is divided into multiple segments with different electrical coupling states. The first shield line is electrically coupled to the first bit line to suppress noise, while the second shield line is not electrically coupled to prevent noise propagation to other regions. This segmentation allows different portions of the shield line to perform different functions.
Solution Approach 2:
Different regions of the shield line are given different electrical coupling properties according to their specific functional requirements. The first shield line in the first region has electrical coupling for noise suppression, while the second shield line in the second region lacks electrical coupling to prevent noise propagation. This local differentiation resolves the contradiction between noise suppression and operational stability.
2Object-affected harmful factors
If shield lines are continuously connected across regions, then noise suppression is improved, but noise spreads across different regions
Solution Approach 1:
The shield line structure is segmented into multiple independent sections. The first shield line is confined to the first region and electrically coupled only to the first bit line, while the second shield line is confined to the second region and not electrically coupled. This segmentation prevents noise from spreading across regions while maintaining local noise suppression where needed.
Solution Approach 2:
The electrical coupling between shield lines and bit lines is selectively extracted or removed in certain regions. By not electrically coupling the second shield line to the second bit line, the patent prevents noise from being transferred to other regions, thereby containing noise within localized areas.
3Object-affected harmful factors
If additional shield lines are added to suppress noise, then noise suppression is improved, but device complexity increases
Solution Approach 1:
Instead of adding multiple continuously connected shield lines, the patent segments the shield line function into multiple independent sections. Each segment serves a specific purpose: the first shield line for noise suppression with electrical coupling, and the second shield line for noise containment without electrical coupling. This segmentation achieves comprehensive noise control without the complexity of a continuously connected multi-region shield line system.
Data Source
AI summary
According to one embodiment, a semiconductor memory includes a first chip including a substrate and a second chip bonded to the first chip. The second chip includes a first region including the memory cell array and the first shield line, and a second region including a second shield line. The first shield line is provided between the first chip and a memory cell array. The second shield line is provided in a same layer as the first shield line, and is not electrically coupled to the first shield line.