NAND Flash Memory Side-Tunneling Control Gate Design

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Solution Overview

Problem

Existing nonvolatile memory systems, particularly NAND flash memory arrays, face compatibility issues due to different standards and inefficiencies in programming and erasing processes, which affect data storage and retrieval across various devices.

Innovation Solution

The implementation of a NAND flash memory array design featuring floating gates with control gates on both sides, utilizing side-tunneling mechanisms facilitated by tunnel and blocking dielectric layers, allows for efficient electron tunneling and reduced wear on dielectric layers by alternating tunneling directions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional single-sided control gate programming is used, then the programming process is simpler, but the dielectric layers experience excessive wear and charge trapping

Engineering Contradiction:

Improveprogramming process simplicityVSAvoiddielectric layer durability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The single control gate is segmented into two separate control gates positioned on opposite sides of the floating gate. This segmentation allows the programming operation to be distributed across two dielectric interfaces, reducing the wear and charge trapping accumulation at any single interface while maintaining the overall programming functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of applying programming voltage from one side through a thick dielectric layer, the invention applies voltage from both sides through thinner dielectric layers. This inverted approach of using dual-sided symmetric voltage application reduces the electric field stress on each individual dielectric layer, thereby reducing wear and charge trapping while achieving the same programming effect.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If thicker dielectric layers are used to prevent charge trapping, then data retention is improved, but tunneling efficiency decreases

Engineering Contradiction:

Improvedata retentionVSAvoidprogramming speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The invention transitions from a one-dimensional tunneling path (single control gate through thick dielectric) to a two-dimensional symmetric structure with control gates on both sides. This dimensional change allows the use of thinner dielectric layers on each side while maintaining adequate charge retention, as the combined effect of two thinner layers provides both sufficient tunneling efficiency and adequate charge trapping prevention.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention changes the dielectric layer thickness parameter from a single thick layer to multiple thinner layers. By reducing the thickness of each individual dielectric layer while increasing the number of layers, the tunneling efficiency is improved (exponential dependence on thickness) while the overall charge retention is maintained through the cumulative effect of multiple layers.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If higher programming voltages are applied to speed up programming, then productivity is improved, but dielectric wear and charge trapping increase

Engineering Contradiction:

Improveprogramming speedVSAvoiddielectric wear

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

Instead of applying a single excessive voltage through one thick dielectric layer, the invention applies moderate voltages through two thinner dielectric layers. Each layer experiences reduced electric field stress, preventing excessive wear and charge trapping, while the combined effect achieves the desired programming speed through distributed partial actions.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances data storage efficiency by enabling reliable programming and erasing across different standards, reduces wear on dielectric layers, and maintains data integrity by minimizing charge trapping and leakage.

Implementation Method 1

generate a voltage difference between the first control gate and the floating gate that is sufficient to produce electron tunneling between the first control gate and the floating gate

Methodology Applied

Scientific EffectElectron tunneling: Electron Beam

Implementation Method 2

the gate dielectric layer including a blocking layer

Methodology Applied

Scientific EffectBlocking electron tunneling: Dielectric

Data Source

PatentUS7512005B2NAND memory with side-tunneling

Publication Date: 2009.03.31 SANDISK TECHNOLOGIES LLC

AI summary

A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.