NAND SLC Buffer Reconfiguration for Runtime Capacity Tradeoffs

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Solution Overview

Problem

Existing storage systems lack user-configurable control over the size of SLC buffers in NAND storage devices, leading to a fixed tradeoff between performance and capacity, and require hardware re-provisioning for capacity changes, risking data loss and filesystem corruption.

Innovation Solution

Implementing a user-configurable SLC buffer size adjustment technology that allows users to dynamically adjust SLC buffer sizes at runtime without data loss, using a host software component to create a padding file or partition for capacity placeholder, enabling seamless performance-capacity tradeoffs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the SLC buffer size is increased to improve performance, then the available storage capacity is reduced

Engineering Contradiction:
ImproveperformanceVSAvoidstorage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements a dynamic SLC buffer size adjustment mechanism that allows the buffer size to be modified at runtime based on user needs and system conditions. The controller can dynamically convert between SLC and MLC regions without hardware re-provisioning, enabling the system to adapt the performance-capacity tradeoff dynamically rather than being fixed at manufacturing.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of storage cells by converting between SLC (single-level cell) and MLC (multi-level cell) modes. This parameter change allows the same physical hardware to provide different performance and capacity characteristics, with SLC offering higher performance and MLC offering higher capacity, and the conversion can be performed dynamically.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the SLC buffer size is adjusted by hardware re-provisioning, then the performance can be optimized, but data loss and filesystem corruption occur

Engineering Contradiction:
ImproveperformanceVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary actions by creating a padding file or partition before adjusting the SLC buffer size. This placeholder reserves the necessary space in advance, allowing the controller to safely convert storage regions without risking data loss. The filesystem is kept consistent throughout the process, and data is preserved while the performance characteristics are adjusted.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the SLC buffer size is fixed at manufacturing, then the device complexity is reduced, but the adaptability to different user needs is limited

Engineering Contradiction:
Improvedevice complexityVSAvoidadaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements multi-functionality by enabling the same storage device to serve different performance and capacity requirements through software-controlled configuration. The controller can operate in multiple modes (different SLC buffer sizes) without requiring different hardware designs, making a single device adaptable to various user needs and application scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12602182B2User configurable SLC memory size
Publication Date: 2026.04.14 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US12602182B2 patent drawing
  • US12602182B2 patent drawing
  • US12602182B2 patent drawing

AI summary

An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.