NAND Memory LLR Remapping for Asymmetric LDPC Decoding Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND memory devices experience hard errors due to degradation over time and defects, leading to asymmetric bit flips that are detrimental to LDPC decoder performance, particularly at end-of-life program erase cycles, where the probability of bit flips from '1' to '0' differs from '0' to '1', causing errors that conventional error correction methods struggle to address effectively.
Innovation Solution
A method is introduced to detect and correct asymmetric hard errors by estimating bit error rates (BER) and using single-level cell reads to identify hard error regions, which informs an optimal log-likelihood ratio (LLR) mapping to improve the correction capability of the LDPC decoder, specifically by generating lookup tables for BER estimation and applying the optimal LLR mapping only to affected bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used for NAND memory devices at end-of-life, then decoding is performed using standard LDPC decoders, but hard errors with asymmetric bit flips cause decoding failures and increased latency
Solution Approach 1:
The patent performs preliminary actions by estimating BER for hard errors and channel errors before decoding, identifying hard error regions using SLC reads, and pre-computing optimal LLR mapping adjustments. This preparation allows the decoder to quickly apply targeted corrections during the actual decoding process, reducing overall latency while improving reliability for asymmetric hard errors in end-of-life NAND memory devices.
2Reliability
If standard LDPC decoding is applied to asymmetric hard errors, then general decoding is performed, but the asymmetric nature of bit flips (different BER for 1→0 vs 0→1) reduces correction effectiveness
Solution Approach 1:
The patent applies local quality by making the LLR mapping error correction adaptive and location-specific. Instead of uniform error correction across all bits, the system identifies hard error regions using SLC reads and applies differentiated LLR adjustments only to affected bits. The correction strength and direction (adding or subtracting from LLR values) is tailored to the specific asymmetric error pattern detected in each region, improving decoding success while managing complexity through targeted intervention.
3Reliability
If multiple recovery attempts are made for hard errors, then error correction is attempted repeatedly, but the number of required RAISE or RAID recoveries increases latency and reduces productivity
Solution Approach 1:
The patent implements feedback by using SLC read results to identify hard error regions and estimate BER, then using this information to adjust LLR mapping for subsequent decoding attempts. The system continuously monitors decoding success and adapts the error correction strategy based on the detected error patterns, reducing the need for multiple recovery attempts and improving data retrieval efficiency while maintaining high reliability.
Data Source
AI summary
Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.