NAND SLC Programming Without Pre-Charge Between Program Loops
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Solution Overview
Problem
Conventional NAND memory devices suffer from low bandwidth and high power consumption, making them unsuitable as a viable alternative to high bandwidth memory (HBM) devices, particularly in applications requiring rapid data access and low power consumption, such as large language models.
Innovation Solution
A high bandwidth flash (HBF) package is developed with a single bit per memory cell (SLC) programming operation, where memory holes are not pre-charged between program loops, and the programming voltage is incremented in small steps (≤0.2 V) until a verify operation passes or a maximum voltage (≤17 V) is reached, ensuring threshold voltages below 2 V and a threshold voltage window of ≤0.5 V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional NAND memory devices are used, then cost is reduced compared to DRAM, but bandwidth is too low and power consumption is too high to be viable
Solution Approach 1:
The patent changes the programming voltage parameter by incrementing it in small steps (≤0.2 V) between program loops instead of using conventional fixed voltage programming. This parameter modification enables tighter threshold voltage control and reduces the number of programming iterations required, thereby increasing bandwidth while maintaining low power consumption in non-volatile memory devices
2Productivity
If pre-charging is performed between program loops, then programming reliability is improved, but bandwidth is reduced due to additional operation time
Solution Approach 1:
The patent extracts and eliminates the pre-charging operation from the programming sequence between program loops. By removing this time-consuming step and compensating through optimized voltage incrementation and verification, the patent achieves high bandwidth operation without sacrificing programming reliability in non-volatile memory devices
3Productivity
If programming voltage is increased to improve programming speed, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by applying programming pulses in discrete, controlled intervals with small voltage increments (≤0.2 V) between pulses. This periodic programming approach, combined with verification operations, achieves fast programming speeds while minimizing power consumption by avoiding continuous high-voltage application in non-volatile memory devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances bandwidth and reduces power consumption, providing a viable alternative to HBM devices with improved read performance and low power consumption, suitable for large language model operations.
Implementation Method 1
applying a programming pulse to the selected word line and then conducting a verify operation
Implementation Method 2
conducting a verify operation to check if programming is complete
Data Source
AI summary
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines and memory holes. The memory device also includes circuitry for programming the memory cells of a selected word line of the plurality of word lines to a single bit per memory cell format. The circuitry is configured to, in a first program loop, apply a programming pulse to the selected word line and then conduct a verify operation. Then, without pre-charging the memory holes after the verify operation of the first program loop, in a second program loop, the circuitry is configured to apply a programming pulse to the selected word line and then conduct a verify operation.