NAND Flash Spiking Neural Network for Parallel Synaptic Current Routing
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Solution Overview
Problem
The challenge of combining currents from individual synaptic memories in NAND flash arrays is difficult due to the series connection of synaptic cells, making it hard to handle multiple simultaneous inputs in a spiking neural network (SNN) effectively.
Innovation Solution
A spiking neural network device utilizing a NAND flash memory as a synaptic memory, incorporating a string select transistor, word line decoder, sensing circuits, and switch transistors to manage multiple simultaneous inputs, enabling efficient synaptic weight storage and computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If synaptic cells are connected in series in NAND flash arrays to provide high data capacity and density, then storage capacity is improved, but the ability to combine currents from individual synaptic memories for processing multiple simultaneous inputs deteriorates
Solution Approach 1:
The patent divides the series-connected synaptic cells into parallel groups by introducing string select transistors and ground select transistors. Each group of synaptic cells can be independently selected and connected to bit lines through the string select transistor, while the ground select transistor controls the connection to ground. This segmentation allows multiple groups to operate simultaneously without current combination issues, resolving the contradiction between high capacity and current combining capability.
Solution Approach 2:
The patent introduces string select transistors and ground select transistors as intermediary components between the synaptic cells and bit lines. These transistors act as switches that can be controlled independently to route currents from different synaptic cell groups to different bit lines simultaneously. This intermediary mechanism enables the system to handle multiple simultaneous inputs while maintaining the series connection structure for high capacity storage.
2Productivity
If more synaptic cells are added to increase network complexity and computational capability, then computational capability is improved, but device complexity and difficulty of operation worsen
Solution Approach 1:
The patent designs the NAND flash memory structure to serve multiple functions: storage of synaptic weights, selection of synaptic groups, and current routing. The string select transistors and ground select transistors are integrated directly into the memory array, allowing the same physical structure to perform both storage and computational routing functions. This multi-functionality reduces overall device complexity while supporting increased computational capability through software control of the transistor switches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient integration and computation of multiple simultaneous inputs in a spiking neural network, enhancing the performance and scalability of neuromorphic computing.
Implementation Method 1
each sensing circuit configured to generate an output spike according to a current transmitted through the bit line when a corresponding word line is selected
Data Source
AI summary
A spiking neural network device comprises at least one NAND cell string including a first NAND cell string that includes a string select transistor and a plurality of nonvolatile memory cells between a bit line and a ground select line, a string control circuit configured to generate a string selection signal to turn on the string select transistor in response to an input spike, a word line decoder configured to generate a word line selection signal for selecting a word line of a plurality of word lines for each of the plurality of nonvolatile memory cells in response to the input spike, a plurality of sensing circuits connected to the bit line, respectively corresponding to the plurality of word lines, each sensing circuit configured to generate an output spike according to a current transmitted through the bit line when a corresponding word line is selected, a plurality of switch transistors, each configured to connect one of the plurality of sensing circuits to the bit line according to a switch selection signal, and a switch decoder configured to generate a switch selection signal in synchronization with the word line selection signal for a selected word line.