NAND Flash Soft-Bit Restoration for Reliable TLC and QLC Reads

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Solution Overview

Problem

Existing memory systems equipped with nonvolatile memory, such as NAND flash memory, face challenges in efficiently controlling and correcting errors, particularly in multi-bit storage systems like TLC (Triple Level Cell) and QLC (Quad Level Cell) where threshold voltage distributions overlap, leading to unreliable data retrieval.

Innovation Solution

The proposed memory system incorporates a nonvolatile memory that outputs hard bit data and soft bit data in response to specific command sets, allowing for error correction processes. The system includes an ECC circuit for encoding and decoding data, and an SB restoration circuit for restoring soft bit data from hard bit data and compressed soft bit data, enabling reliable data retrieval even in overlapping threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-bit storage systems (TLC/QLC) are used to increase storage capacity, then storage density is improved, but threshold voltage distribution overlap increases leading to unreliable data retrieval

Engineering Contradiction:
Improvestorage capacityVSAvoiddata retrieval reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments soft bit data into multiple groups (first group, second group, third group) corresponding to different threshold voltage distribution regions. This segmentation allows independent processing and restoration of soft bit data from different regions, improving overall data retrieval reliability in multi-bit storage systems by addressing the overlap problem region-by-region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary restoration of soft bit data from compressed soft bit data and hard bit data before final data retrieval. By restoring soft bit data in advance using the restoration circuit, the system prepares corrected data that can be used for more reliable error correction, addressing the reliability issue before it affects data retrieval.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If soft bit data is restored from compressed soft bit data and hard bit data, then data retrieval reliability is improved, but device complexity increases due to additional restoration circuits

Engineering Contradiction:
Improvedata retrieval reliabilityVSAvoidrestoration circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The restoration circuit is designed to perform multiple functions: it restores soft bit data from compressed soft bit data and hard bit data, and can handle multiple groups of soft bit data corresponding to different threshold voltage regions. This multi-functionality reduces the need for separate restoration circuits for each region, thereby managing device complexity while maintaining improved reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If hard bit data and soft bit data are used for error correction, then error correction capability is improved, but processing time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary restoration of soft bit data from compressed soft bit data and hard bit data before the error correction process. By having the restoration circuit prepare restored soft bit data in advance, the actual error correction process can use this pre-restored data directly, reducing the time required during the critical error correction phase while maintaining improved error correction capability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250147842A1Memory system and nonvolatile memory
Publication Date: 2025.05.08 KIOXIA CORP
  • US20250147842A1 patent drawing
  • US20250147842A1 patent drawing
  • US20250147842A1 patent drawing

AI summary

According to one embodiment, a memory system includes a nonvolatile memory that includes memory cells. The nonvolatile memory outputs, to a memory controller, first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit, in response to a first command set. The nonvolatile memory outputs, to the memory controller, the first hard bit data, the second hard bit data, the third hard bit data, first soft bit data related to the first bit, second soft bit data related to the second bit, and third soft bit data related to the third bit, in response to a second command set.