NAND Flash Soft Decoding With Dynamic Candidate Enumeration
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Solution Overview
Problem
Current NAND flash devices face challenges in improving decoding reliability and reducing decoding complexity, especially in high bit error rate scenarios, due to the complexity of existing decoding algorithms and hardware implementation.
Innovation Solution
The implementation of an iterative soft decoding method that uses a candidate list and dynamic enumeration size adaptation to reduce decoding complexity while maintaining high reliability, specifically for half product codes and half folded-product codes, by performing joint component soft decoding and utilizing historical candidate lists.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional soft decoding algorithms are used in NAND flash devices, then decoding reliability can be maintained, but decoding complexity increases significantly
Solution Approach 1:
The patent segments the decoding process into multiple iterations, where each iteration focuses on a specific candidate list of error patterns. Instead of exhaustively searching all possible error patterns, the algorithm divides the search space into manageable segments (candidate lists), processing them in sequential iterations until convergence or maximum iterations are reached.
Solution Approach 2:
The patent performs preliminary action by pre-generating and sorting candidate lists of error patterns based on their likelihood metrics before the main decoding process. This preliminary sorting and filtering of candidates reduces the search space for subsequent iterations, eliminating the need to evaluate all possible error patterns during the actual decoding operation.
2Measurement precision
If exhaustive error pattern search is performed, then decoding accuracy improves, but decoding latency increases
Solution Approach 1:
The patent applies partial action by performing decoding on a selected subset of candidate error patterns rather than exhaustively searching all possible patterns. The candidate lists are prioritized based on likelihood metrics, allowing the decoder to focus computational resources on the most promising candidates first, achieving sufficient accuracy without complete enumeration.
Solution Approach 2:
The patent introduces dynamics by adaptively adjusting the number of iterations and candidate list sizes based on the specific data being decoded and the observed error patterns. The algorithm can terminate early when convergence is detected or when the maximum number of iterations is reached, making the decoding process flexible rather than rigidly exhaustive.
3Reliability
If more enumeration steps are performed in each iteration, then error correction capability improves, but computational complexity increases
Solution Approach 1:
The patent segments the enumeration process into multiple iterations with progressively refined candidate lists. Each iteration enumerates error patterns up to a certain weight (number of bit flips), and the candidate lists from previous iterations are carried forward and refined, dividing the complex enumeration task into manageable sequential segments.
Solution Approach 2:
The patent implements feedback by using the results from each iteration to inform and adjust subsequent iterations. The candidate lists are updated based on the performance and convergence observations from previous iterations, allowing the algorithm to adapt the enumeration depth and candidate selection criteria dynamically rather than using a fixed exhaustive approach.
Data Source
AI summary
A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.