NAND Soft Read Sequencing for Lower Latency ECC
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Solution Overview
Problem
Conventional methods for collecting soft-bit information in NAND flash memory increase latency and degrade performance due to increased traffic on the data I/O bus, affecting the quality of service in solid state drives (SSDs).
Innovation Solution
Implementing progressive data output by initially sending hard-bit information and withholding certain soft-bit information from the controller, conducting error corrections on the hard-bit information first, and requesting additional soft-bit information only if necessary, thereby reducing latency and data bus traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft-bit information is collected using conventional approaches, then error correction capability is improved, but read latency increases and performance deteriorates
Solution Approach 1:
The patent segments soft-bit information into multiple groups (first group and second group) and transmits them at different times. The first group is transmitted with hard-bit information immediately, while the second group is transmitted later only if error correction is needed, thereby reducing initial read latency while maintaining error correction capability.
Solution Approach 2:
The patent performs preliminary error correction on hard-bit information using the first group of soft-bit information before requesting additional soft-bit information. This preliminary action allows many reads to complete without needing the full soft-bit information, reducing overall latency.
2Reliability
If soft-bit information is transferred over the data I/O bus, then error correction capability is improved, but data bus traffic increases and performance decreases
Solution Approach 1:
The patent extracts only the necessary portion of soft-bit information (the first group) that is needed for initial error correction and transmits it over the data I/O bus. The second group is withheld and only transmitted if the preliminary error correction fails, thereby reducing data bus traffic while maintaining adequate error correction capability.
Solution Approach 2:
The patent uses partial soft-bit information (first group only) for preliminary error correction instead of transmitting all soft-bit information. This partial action is sufficient for many correction cases, reducing bus traffic while maintaining performance.
Data Source
AI summary
Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.