NAND Soft-Read Progressive Output for Lower ECC Latency
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Solution Overview
Problem
Conventional methods for collecting soft-bit information in NAND memory devices increase latency, negatively impacting performance and quality of service (QoS), and lead to delays in transmitting this information over shared data I/O buses.
Innovation Solution
Implementing progressive soft-read operations with multiple strobes (e.g., 3-strobe, 5-strobe, 7-strobe) that generate soft-bit information in addition to hard-bit information, allowing for initial withholding of soft-bit data to reduce latency and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft-bit information is collected using conventional approaches, then error correction capability is improved, but latency increases and performance deteriorates
Solution Approach 1:
The patent segments soft-bit information collection into multiple progressive stages (e.g., 3-strobe, 5-strobe, 7-strobe reads) rather than collecting all soft-bit information at once. Each stage provides increasing error correction capability while maintaining acceptable latency by allowing the controller to process data incrementally and request additional soft-bit information only if needed.
Solution Approach 2:
The controller performs preliminary error correction using hard-bit information and initial soft-bit information before requesting additional soft-bit data. This preliminary action allows the system to handle most cases with minimal latency while reserving the option to collect more soft-bit information only when error correction is needed.
2Reliability
If soft-bit information is transmitted over shared data I/O bus, then error correction capability is improved, but transmission delays increase and performance reduces
Solution Approach 1:
The patent transmits only the necessary portion of soft-bit information over the shared data I/O bus rather than all soft-bit data. The controller requests specific amounts of soft-bit information (e.g., 1-bit, 2-bits) based on error correction needs, reducing bus traffic and transmission delays while maintaining adequate error correction capability.
Solution Approach 2:
The memory device performs self-service by conducting multiple progressive read operations internally to collect soft-bit information before transmission. This reduces the burden on the shared I/O bus by pre-processing data locally and only transmitting essential information when requested.
3Measurement precision
If multiple strobes are used for soft-read operations, then soft-bit information quality is improved, but data collection time increases
Solution Approach 1:
The patent implements dynamic soft-read operations where the number of strobes (3, 5, or 7) is adaptively selected based on error correction requirements and performance conditions. The system dynamically adjusts the read operation intensity to match the actual need, providing high precision when necessary while maintaining fast operation when error rates are low.
Solution Approach 2:
The system changes operational parameters by varying the number of strobes used in soft-read operations. By adjusting this parameter based on error correction needs, the patent achieves high soft-bit information quality when required while minimizing data collection time during normal operating conditions.
Data Source
AI summary
Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.