3D NAND Source Line Biasing to Reduce Capacitive Loading
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Solution Overview
Problem
Existing flash memory systems face inefficiencies in programming and reading operations due to the need for precise threshold voltage control across a wide voltage window, especially when dealing with multi-state data storage, and the challenge of erasing data in large blocks which can be cumbersome and slow.
Innovation Solution
A memory circuit and method that utilize an array of non-volatile memory cells with NAND strings connected to local and global source lines, where decoding circuitry selects blocks in multi-block groups and driver circuitry applies source line voltage and operating voltages to optimize memory operations, reducing capacitive loading and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If blocks are selected in multi-block groups with shared source lines, then decoding efficiency is improved, but capacitive loading on source lines increases
Solution Approach 1:
The memory array is divided into multiple blocks that can be independently selected and operated. By segmenting the memory into blocks with shared source lines, the system can decode multiple blocks simultaneously while managing capacitive loading through selective activation. This segmentation allows parallel processing of multiple blocks without overwhelming the source line driver capability.
Solution Approach 2:
The patent applies partial action by activating only the necessary word lines and blocks within the selected multi-block groups, rather than activating all blocks. This selective activation reduces the effective capacitive loading on source lines while still achieving improved decoding efficiency through multi-block selection. The system performs exactly the number of operations needed - no more, no less.
2Use of energy by moving object
If source line voltage is applied to unselected blocks, then capacitive loading is reduced, but power consumption increases
Solution Approach 1:
The patent applies equipotentiality by setting the source line voltage to the same potential level for both selected and unselected blocks within a multi-block group. By maintaining equipotential conditions across all blocks sharing a common source line, the system eliminates potential differences that would cause capacitive charging currents. This reduces the effective capacitive loading on the source line driver while managing power consumption through selective word line activation.
3Speed
If multiple blocks are decoded simultaneously, then operation speed is improved, but driver circuit complexity increases
Solution Approach 1:
The driver circuitry is designed with multi-functionality to handle both single-block and multi-block operations using the same basic circuit structures. The universal driver circuits can selectively activate different combinations of blocks within predefined multi-block groups, achieving high-speed parallel operation without requiring completely separate driver circuits for each block. This multi-functionality reduces overall system complexity while maintaining high operation speed.
Data Source
AI summary
Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.