3D NAND Memory Source Isolation Structure for Leakage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining operational reliability due to leakage currents, which can lead to deterioration in performance and stability, particularly in three-dimensional structures.
Innovation Solution
The proposed semiconductor memory device incorporates a source stack structure, source insulating layer, and isolation insulating layer, along with a vertical structure and slit partitioning, to effectively block current leakage and enhance manufacturing process stability. This configuration includes a peripheral circuit structure, interlayer insulating layers, conductive layers, and sacrificial layers, which are alternately stacked and processed to form a reliable memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional NAND-type memory structure is adopted to achieve high integration, then storage capacity increases, but leakage current increases leading to deteriorated operational reliability
Solution Approach 1:
The memory device is divided into distinct functional regions: a first region containing the memory block with high integration three-dimensional structure, and a second region containing the peripheral circuit. An isolation insulating layer is introduced between these regions to segment the current paths, preventing leakage current from affecting the peripheral circuit while maintaining high storage capacity in the memory block.
Solution Approach 2:
An isolation insulating layer is introduced as an intermediary element between the memory block and peripheral circuit. This isolation layer acts as a mediator that blocks leakage current from the three-dimensional memory structure from reaching the peripheral circuit, thereby protecting operational reliability without compromising the high integration benefits.
2Quantity of substance
If a three-dimensional structure is used to increase integration density, then more memory cells fit in the device, but manufacturing process stability deteriorates
Solution Approach 1:
The device is segmented into a memory block region and a peripheral circuit region, with the isolation insulating layer providing a clear manufacturing boundary. This segmentation allows different manufacturing processes to be optimized independently for each region, improving overall manufacturing stability while maintaining high integration density in the memory block.
Solution Approach 2:
The isolation insulating layer serves as an intermediary that simplifies the manufacturing process by providing a defined interface between the complex three-dimensional memory structure and the peripheral circuit. This intermediary layer makes it easier to control current flow and manage thermal effects during manufacturing, thereby improving process stability.
3Ease of operation
If leakage current is allowed to flow in the peripheral circuit region, then device operation continues, but operational reliability deteriorates due to current leakage
Solution Approach 1:
The isolation insulating layer acts as an intermediary barrier that selectively blocks leakage current in the peripheral circuit region while maintaining normal device operation. This isolation layer prevents harmful leakage currents from affecting the peripheral circuit, thereby protecting operational reliability without interrupting legitimate device operations.
Solution Approach 2:
Different regions of the device are given different electrical characteristics: the memory block region allows current flow for normal operation, while the peripheral circuit region is isolated to prevent leakage current. This local differentiation of electrical properties enables the device to operate normally while protecting against reliability deterioration from leakage.
Data Source
AI summary
A semiconductor memory device includes: a substrate; a source stack structure and a source insulating layer disposed over the substrate to be spaced apart from each other; an isolation insulating layer disposed between the source stack structure and the source insulating layer; a first stack structure disposed over the source stack structure; a second stack structure disposed over the source insulating layer; a vertical structure penetrating the first stack structure and a portion of the source stack structure; and a lower contact penetrating the source insulating layer.