3D NAND Source-Line Contact Structure With Laser-Annealed Semiconductor Layers
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Solution Overview
Problem
The increasing integration of semiconductor storage devices leads to challenges in connecting the upper end of semiconductor layers to source lines due to the difficulty in removing gate insulating films from through via holes with high aspect ratios, and the risk of metal atom diffusion during heat treatment, affecting device performance.
Innovation Solution
The method involves forming semiconductor layers with high impurity concentration at the upper end of semiconductor layers using laser annealing and planarizing the surface with insulating layers to prevent metal atom diffusion, allowing for easier connection to source lines without heat-induced disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate insulating films are removed from through via holes with high aspect ratios to improve connectivity, then electrical connection to source lines is improved, but manufacturing difficulty increases due to the high aspect ratio removal process
Solution Approach 1:
The gate insulating film is removed from the through via hole before forming the semiconductor layer, performing the difficult removal operation at an earlier stage when the via hole is more accessible and the aspect ratio challenge is more manageable, rather than attempting removal after layer stacking
2Reliability
If heat treatment is applied to form high impurity concentration semiconductor layers, then electrical conductivity is improved, but metal atom diffusion occurs causing device performance degradation
Solution Approach 1:
A barrier layer is formed at the interface between the semiconductor layer and the source line before heat treatment, creating a preventive structure that blocks metal atom diffusion pathways and protects against the harmful effects of diffusion during subsequent thermal processing
Solution Approach 2:
The barrier layer acts as an intermediary material between the semiconductor layer and source line, mediating the interface to prevent direct contact and diffusion between metal atoms while still allowing electrical connection through the high impurity concentration semiconductor region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the manufacture of semiconductor storage devices with improved electrical connectivity and reduced risk of metal atom diffusion, ensuring stable device operation.
Implementation Method 1
forming semiconductor layers with high impurity concentration at the upper end of semiconductor layers using laser annealing
Data Source
AI summary
A semiconductor storage device includes first and second stacks, and first to fourth semiconductor layers. The first stack includes first conductive layers and first insulating layers alternately stacked in a first direction. The first semiconductor layer extends through the first stack. The second semiconductor layer extends in a second direction above the first stack and connected to the first semiconductor layer. The second stack includes second conductive layers and second insulating layers alternately stacked in the first direction. The first and second stacks are arranged in a third direction. The third semiconductor layer extends through the second stack. The fourth semiconductor layer extends in the second direction above the second stack and connected to the third semiconductor layer. A third conductive layer is in contact with upper surfaces of the second and fourth semiconductor layers. The second and fourth semiconductor layers are separated from each other in the third direction.