NAND Memory Array Source-Side Segmentation for Faster Access
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Solution Overview
Problem
Current memory array structures in NAND flash memory devices face challenges in efficiently segmenting memory cells for improved access speeds and power management due to limitations in source-side segmentation in source-last fabrication schemes.
Innovation Solution
The implementation of source-side segmentation in memory array structures, where select gates are programmed to have unique threshold voltages for each sub-block of memory cells, allowing for independent control and reducing loading on access lines, enabling lower RC values and improved access speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If source-side segmentation is implemented in source-last fabrication schemes, then access speeds are improved and power consumption is reduced, but device complexity increases due to additional select gates and threshold voltage programming requirements
Solution Approach 1:
The memory array is divided into multiple sub-blocks with independent select gates (SGS0, SGS1, etc.) that can be independently controlled. Each sub-block can be selectively accessed or electrically floated, enabling parallel operations and reduced access times for specific memory regions without requiring the entire array to be accessed.
Solution Approach 2:
Different sub-blocks are assigned different threshold voltages (Vt0, Vt1, etc.) through independent select gate programming, creating local variations in electrical characteristics. This allows specific sub-blocks to be optimized for different functions (e.g., fast access, power saving, or electrical floating) while maintaining uniform memory cell structures throughout the array.
2Ease of operation
If select gates are programmed with unique threshold voltages for each sub-block, then independent control of sub-blocks is achieved and loading on access lines is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The select gates are pre-programmed with distinct threshold voltages during the fabrication process using controlled doping or charge trapping techniques. This preliminary programming establishes the independent control capability before the memory device is operational, allowing sub-blocks to be selectively activated or floated without requiring complex runtime programming operations.
Solution Approach 2:
The threshold voltage of select gates is used as a controllable parameter to differentiate between sub-blocks. By adjusting the doping concentration, charge trap density, or gate dielectric properties during fabrication, each select gate group is assigned a unique threshold voltage that enables independent electrical control and floating of corresponding memory sub-blocks.
3Use of energy by moving object
If sub-blocks are electrically floated to reduce power consumption, then energy efficiency is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The select gates are designed with dynamic threshold voltage characteristics that can be adjusted between active and floating states. By applying control voltages to the select gate control lines, the threshold voltage of each select gate can be dynamically shifted to either enable conduction (active state) or block conduction (floating state), allowing power consumption to be dynamically optimized based on access patterns.
Solution Approach 2:
The power consumption reduction is achieved by electrically floating (isolating) inactive sub-blocks from the rest of the circuit using the select gates. The select gates act as switches that extract or remove the electrical connection to sub-blocks that are not currently being accessed, preventing leakage currents and reducing overall power consumption without requiring additional power management circuitry.
Data Source
AI summary
Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.