3D NAND Memory Stack Bonding for Dense Fast Access
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Solution Overview
Problem
Existing memory technologies, such as DRAM, NAND, and MRAM, face limitations in terms of density, speed, and cost, failing to provide a balanced combination of these critical performance metrics.
Innovation Solution
A memory structure comprising a NAND block with a staircase arrangement of oxide layers, vias, and bonding interconnects, allowing for face-to-face bonding with a logic wafer and vertical stacking, utilizing non-adhesive bonding techniques and dielectric embedding to enhance connectivity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory structures (DRAM, NAND, MRAM) are used, then each achieves certain performance metrics, but they cannot simultaneously provide high density, high speed, and low cost
Solution Approach 1:
The patent transitions from planar memory architectures to three-dimensional stacked memory structures. Multiple memory layers are vertically stacked with interconnect structures enabling both vertical and horizontal data pathways, effectively utilizing the third dimension to increase storage density while maintaining fast access through multiple simultaneous operation channels.
Solution Approach 2:
The memory structure is divided into multiple functional layers including memory cells, interconnect layers, and bonding interfaces. Each layer can be independently optimized and manufactured, allowing parallel processing and simultaneous read/write operations across different segments, thereby increasing both density and speed.
2Quantity of substance
If complex bonding and interconnect structures are implemented to achieve high density stacking, then manufacturing precision requirements increase
Solution Approach 1:
The bonding interconnect structures are designed to self-align during the stacking process. Complementary electrode patterns and conductive via arrangements automatically position components correctly through geometric constraints and material properties, reducing the need for high-precision external alignment equipment and processes.
Solution Approach 2:
Dielectric materials and bonding layers serve as intermediary elements between metal interconnects. These intermediaries provide tolerance buffering, allowing slight misalignments to be compensated while maintaining electrical connectivity, thereby reducing the stringency of precision requirements.
Data Source
AI summary
A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.