3D NAND Memory Stack Layout for Peripheral Circuit Integration
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Solution Overview
Problem
Existing NAND-type flash memories with three-dimensionally disposed memory cells face challenges in efficiently integrating and connecting the memory cell array with the peripheral circuit, leading to limitations in data storage capacity and operational efficiency.
Innovation Solution
The semiconductor storage device incorporates a multi-layered body with alternately stacked gate electrode layers and insulating layers, along with a semiconductor layer containing p-type and n-type semiconductor portions, to facilitate electrical connections through wirings, thereby enhancing integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally disposed memory cells are used, then data storage capacity is improved, but integration efficiency with peripheral circuit deteriorates
Solution Approach 1:
The memory cell array is divided into multiple blocks, with each block containing a specific number of memory cells. This segmentation allows for modular integration with peripheral circuits, improving both storage capacity and integration efficiency by enabling independent processing and connection of memory blocks to the peripheral circuitry.
2Quantity of substance
If more memory cells are integrated, then data storage capacity is improved, but connection efficiency with peripheral circuit deteriorates
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional stacking, where memory cells are arranged vertically in multiple layers. This dimensional change allows significantly more memory cells to be integrated without proportionally increasing the footprint or connection complexity, as connections are made through vertical vias and stacked architectures rather than extensive lateral routing.
Data Source
AI summary
A semiconductor storage device according to one embodiment includes the first chip and a second chip. The second chip is adhered to the first chip. The second chip includes a multi-layered body, a columnar body, a semiconductor layer, a first wiring, and a second wiring. The columnar body has a first end portion. The semiconductor layer has a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first part along the first end of the multi-layered body and a second part covering the first end portion of the columnar body. The first semiconductor portion and the second semiconductor portion contain impurities forming a p-type semiconductor. The third semiconductor portion contains impurities forming an n-type semiconductor. The first gate electrode layer includes a part overlapping the first semiconductor portion when viewed in a first direction.