3D NAND Memory Array Stack with Sacrificial Channel Etch Stop
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Solution Overview
Problem
Existing memory array fabrication methods face challenges in efficiently forming vertically-stacked memory cells with reliable connections and structural integrity, particularly in NAND architecture, which affects the performance and reliability of integrated circuitry.
Innovation Solution
The method involves forming a memory array using 'gate-last' or 'replacement-gate' processing, where sacrificial materials are used to create vertically-alternating tiers and channels, followed by deposition of transistor materials and conductive lines, ensuring precise etching and integration of charge-blocking and storage regions to form reliable memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory fabrication methods are used, then manufacturing process is simpler, but structural integrity and performance of vertically-stacked memory cells deteriorates
Solution Approach 1:
The patent applies preliminary action by forming sacrificial materials in advance during the fabrication process. These sacrificial materials are strategically placed before the main memory cell structures are completed, allowing for precise control of the final vertical stack geometry. The sacrificial materials are later removed to create the desired channel and gate structures, ensuring structural integrity without requiring complex post-processing steps.
Solution Approach 2:
The patent uses sacrificial materials as intermediary elements during fabrication. These materials serve as temporary mediators that define the spatial relationships between different memory cell components. By using these intermediary sacrificial structures, the process achieves high structural precision without directly forming the final complex geometries in a single step, thereby managing fabrication complexity.
2Reliability
If vertically-stacked memory cells are formed with precise connections, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs sacrificial materials as intermediary structures that define the precise locations where etching should occur. These sacrificial materials act as templates, allowing standard etching processes to achieve high precision by following the predefined sacrificial material geometry. This approach ensures reliable connections between vertically-stacked components without requiring extreme etching precision.
Solution Approach 2:
The patent performs preliminary formation of sacrificial material structures before the critical connection-forming steps. By pre-establishing the spatial framework with sacrificial materials, the subsequent etching and material deposition steps can proceed with standard precision requirements, as the critical alignment has already been established by the sacrificial structures.
3Reliability
If gate-last or replacement-gate processing is used, then performance of memory cells improves, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial materials that define the gate region boundaries before the gate itself is formed. This preliminary structuring enables the gate-last or replacement-gate processing to proceed systematically, with each step building upon the previously established sacrificial framework, thereby managing the increased processing complexity.
Solution Approach 2:
The sacrificial materials serve as intermediary structures that guide the complex gate-last or replacement-gate processing sequence. These intermediaries provide a reference framework that simplifies the coordination of multiple processing steps, allowing the complex gate formation process to be executed with better control and reduced overall device complexity.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.


