3D NAND Stack Structure With Flat Contact Region for Gate Connections
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Solution Overview
Problem
To achieve high integration density in semiconductor devices, existing technologies face challenges in efficiently connecting stacked gate electrodes to peripheral circuits, leading to increased complexity and potential defects.
Innovation Solution
A semiconductor device design featuring a stack structure with alternating interlayer insulating and horizontal layers, including a staircase and flat region in the connection area, with gate contact plugs that contact pads and edge regions, enhancing electrical connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked gate electrodes is increased to achieve high integration density, then integration density is improved, but connection complexity and potential defects increase
Solution Approach 1:
The stack structure is divided into multiple distinct regions (staircase region with multiple steps, flat region, dummy region) that can be independently formed and connected. This segmentation allows complex connections to be broken down into manageable sections, reducing overall connection complexity while maintaining high integration density through the vertical stacking architecture.
Solution Approach 2:
The patent transitions from planar connections to three-dimensional vertical connections by stacking gate electrodes in the vertical direction. The stack structure extends upward with multiple horizontal layers separated by interlayer insulating layers, enabling high integration density without proportionally increasing lateral connection complexity.
2Quantity of substance
If the stack structure extends into the connection region, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The staircase region is formed first with multiple steps at different heights, providing pre-positioned connection points. The flat region is then formed on top of the highest step, and finally the dummy region is added. This preliminary action approach allows each subsequent layer to be formed with reference to the previous structure, reducing cumulative alignment errors and improving manufacturing precision.
Solution Approach 2:
The interlayer insulating layers act as intermediaries between the horizontal layers, providing isolation and reference planes that facilitate precise alignment. These insulating layers are formed between each horizontal layer, creating distinct stages that simplify the positioning and connection processes for subsequent layers.
3Reliability
If multiple gate contact plugs are formed in the connection region, then electrical connectivity is improved, but defect risk increases
Solution Approach 1:
Different regions of the stack structure are assigned different functions: the staircase region provides multiple connection levels, the flat region provides a stable platform for contact plugs, and the dummy region provides additional connection options. This local differentiation allows contact plugs to be strategically positioned in areas with optimal mechanical and electrical properties, improving reliability while minimizing defect risks through careful regional optimization.
Data Source
AI summary
A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.