3D NAND Charge Storage Stack With Selective Etch Gate Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3D-NAND flash memory devices face issues with charge trapping in horizontal inter-poly dielectric (IPD) materials, leading to degraded cell program-erase cycling and unreliable threshold voltage, due to the presence of oxide-nitride-oxide (ONO) materials, which complicates the fabrication process and increases critical dimensions.
Innovation Solution
A fabrication process that forms floating gates with a height equal to adjacent control gates by using oxide materials with varying densities, allowing selective etching to control the height and profile of control gate recesses, thereby minimizing charge trapping and maintaining critical dimensions without additional complex steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide-nitride-oxide (ONO) materials are used as inter-poly dielectric, then charge blocking is achieved, but charge trapping occurs leading to degraded program-erase cycling and unreliable threshold voltage
Solution Approach 1:
The patent removes the problematic nitride layer from the ONO inter-poly dielectric structure, retaining only the oxide layers. This extraction eliminates the charge trapping source while preserving the charge blocking function through the remaining oxide-nitride-oxide structure, thereby improving program-erase cycling reliability.
Solution Approach 2:
The patent converts the harmful charge trapping effect of the nitride layer into a beneficial charge blocking function by strategically positioning the nitride layer only where needed for blocking charges between floating gates and control gates, while eliminating it from regions where it would trap charges and degrade reliability.
2Reliability
If floating gates are made shorter than control gates, then charge blocking is improved, but channel conductance modulation is reduced and cell noise increases
Solution Approach 1:
The patent applies different heights to different parts of the gate structure: floating gates are made shorter than control gates in regions where charge blocking is critical, while extending to full height in regions where channel conductance modulation is needed. This local differentiation optimizes both charge blocking and signal strength.
Solution Approach 2:
The patent resolves the height conflict by transitioning from a single-dimension height parameter to a multi-dimensional gate structure with varying heights at different lateral positions. This allows the floating gates to have shorter sections for charge blocking and longer sections for channel control, eliminating the trade-off.
3Reliability
If additional fabrication steps are added to minimize charge trapping, then reliability improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of the inter-poly dielectric and the charge blocking structure into a single integrated oxide-nitride-oxide layer sequence, eliminating the need for separate charge blocking structures. This merging reduces fabrication steps while achieving both charge trapping prevention and charge blocking functions.
Solution Approach 2:
The oxide-nitride-oxide inter-poly dielectric structure serves multiple functions simultaneously: it provides charge blocking between floating gates and control gates, prevents charge trapping that would degrade reliability, and maintains electrical isolation. This multi-functionality eliminates the need for additional dedicated charge blocking structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances channel conductance modulation, reduces cell noise, and improves reliability by aligning floating and control gates while maintaining device performance and simplifying the fabrication process.
Implementation Method 1
using oxide materials with varying densities, allowing selective etching to control the height and profile of control gate recesses
Data Source
AI summary
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.