3D NAND Stack Structure with Etch-Resistant Support Layers

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Solution Overview

Problem

Conventional methods for forming 3D NAND Flash memory devices result in undesirable deformations and damage, such as tier bending, warping, cracking, and collapse, leading to reliability and durability issues due to the replacement gate or gate last processing methods.

Innovation Solution

The method involves forming an etch-resistant material within the sacrificial material layers to prevent damage during the replacement gate processing, which includes forming a stack structure with insulative and sacrificial material tiers and replacing the sacrificial material with conductive structures, thereby mitigating deformations and enhancing structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If replacement gate or gate last processing methods are used to form stack structures, then memory device fabrication can be achieved, but undesirable deformations and damage occur including tier bending, warping, cracking, and collapse

Engineering Contradiction:
Improvefabrication processVSAvoidstructural integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The method forms a liner material layer on the sacrificial material before forming the stack structure. This preliminary protective layer prevents direct contact between the sacrificial material and subsequent processing steps, thereby preventing deformations and damage to the stack structure during replacement gate processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The liner material acts as an intermediary between the sacrificial material and the stack structure. This intermediate layer transfers and distributes mechanical stresses, preventing direct transmission of damaging forces that would cause tier bending, warping, cracking, or collapse

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If feature packing densities are increased to improve memory density, then more memory cells can be packed, but margins for formation errors decrease leading to more damage

Engineering Contradiction:
Improvememory cell densityVSAvoidformation error margin
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The liner material layer is formed beforehand on the sacrificial material to provide a protective cushion during high-density fabrication. This pre-formed protective layer absorbs and distributes mechanical stresses that would otherwise cause damage when features are closely packed with reduced formation error margins

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12041769B2Methods of forming microelectronic devices
Publication Date: 2024.07.16 MICRON TECHNOLOGY INC
  • US12041769B2 patent drawing
  • US12041769B2 patent drawing
  • US12041769B2 patent drawing

AI summary

A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.