3D NAND Layer Stack Support to Prevent Void Formation
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Solution Overview
Problem
Current NAND flash memory devices face challenges in optimizing the manufacturing process to prevent void formation and improve yield, particularly in the replacement of sacrificial layers, which can lead to broken stacked structures and reduced device performance.
Innovation Solution
The proposed solution involves forming specific shapes and arrangements of members SLTc and SLTd before the stacked interconnect structure is formed, ensuring that sacrificial layers are removed only within these structures, thereby minimizing the risk of void formation and enhancing the manufacturing process efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sacrificial layers are removed during the manufacturing process, then the stacked interconnect structure can be formed, but voids may form and the structure may break
Solution Approach 1:
The patent applies preliminary action by forming the first and second members (SLTc and SLTd) before removing the sacrificial layers. These members are positioned in advance to support the stacked interconnect structure during the sacrificial layer removal process, preventing void formation and structural breakage. The members remain in place during etching operations to maintain structural integrity until the sacrificial layers are completely removed.
2Productivity
If the stacked interconnect structure is formed with multiple layers, then device capacity and integration are increased, but the manufacturing complexity and risk of void formation increase
Solution Approach 1:
The patent segments the support structure into two separate members: the first member (SLTc) positioned between the first and second stacked interconnect structures, and the second member (SLTd) positioned between the second and third stacked interconnect structures. This segmentation allows each member to independently support specific portions of the stacked structure during manufacturing, reducing overall complexity while enabling high device capacity through multiple stacked layers.
3Manufacturing precision
If sacrificial layers are removed completely, then the final interconnect structure is achieved, but voids and manufacturing defects may occur
Solution Approach 1:
The patent implements beforehand cushioning by positioning the first and second members (SLTc and SLTd) in advance to act as protective supports during the sacrificial layer removal process. These members cushion against the formation of voids and prevent structural breakage that would otherwise occur during complete sacrificial layer removal. The members are strategically placed to provide mechanical support exactly where voids are most likely to form during the etching process.
Data Source
AI summary
According to one embodiment, a memory device includes: a first layer stack including first insulating layers arranged in a first direction and spaced apart from one another; second and third layer stacks, each including conductive layers spaced apart from one another and provided at levels of layers identical to the first insulating layers, respectively, and being spaced apart from each other; a memory pillar extending in the first direction in the third layer stack, a portion of the memory pillar intersecting each of the conductive layers functioning as a memory cell; a first member in contact with the first and second layer stacks between the first and second layer stacks and extending in a second direction; and a second member in contact with the second and third layer stacks between the second and third layer stacks and extending in the second direction.