3D NAND Word-Line Stair Layout for Smaller Peripheral Area
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Solution Overview
Problem
The challenge in developing three-dimensional non-volatile memory devices is to reduce chip size while maintaining high integration, as the increase in the number of word lines stacked vertically leads to a larger peripheral circuit area, which contradicts the goal of miniaturization.
Innovation Solution
The solution involves a stacked semiconductor structure where the memory cell array and row decoder are vertically aligned, with pass transistors in a stair-shaped area overlapping the word lines, allowing for a more compact design by reducing the area occupied by the pass transistor circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked vertically increases to increase memory capacity, then the memory capacity is improved, but the area of the peripheral circuit region increases
Solution Approach 1:
The patent applies three-dimensional vertical stacking to arrange the peripheral circuit region underneath the memory cell array, transitioning from a planar two-dimensional layout to a three-dimensional structure. This allows the peripheral circuit and memory cell array to occupy different vertical levels, enabling increased memory capacity through additional word lines without expanding the peripheral circuit area in the planar view.
Solution Approach 2:
The peripheral circuit region is nested underneath the memory cell array in the vertical direction, creating a stacked configuration where one functional region is positioned within the vertical footprint of another. This nesting approach allows both regions to coexist in the same planar area by utilizing the third dimension, thereby preventing the peripheral circuit area from increasing as memory capacity expands.
2Device complexity
If the number of word lines stacked vertically increases to improve integration, then the integration degree is improved, but the chip size increases due to more pass transistors
Solution Approach 1:
The pass transistor circuit is arranged in a vertical stack configuration rather than a planar expansion, utilizing the third dimension to accommodate additional pass transistors required for increased integration. This vertical arrangement allows more pass transistors to be packed into the same chip area by stacking them in multiple layers, thereby improving integration without proportionally increasing chip size.
Solution Approach 2:
The pass transistor circuit is merged with the memory cell array structure by positioning it in the same vertical column region, sharing the same physical space through three-dimensional stacking. This merging allows the pass transistors to be integrated into the existing memory structure footprint, reducing the additional chip area required compared to separate planar arrangements.
Data Source
AI summary
A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.