3D NAND Stair-Step Tread Formation With Self-Aligned Spacers
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and reduced masking steps, particularly in the stair-step structures of NAND architecture, which affect the scalability and performance of memory arrays.
Innovation Solution
The method involves forming anisotropically-etched spacers in the stair-step region to create multiple different-depth treads in the conductive tiers, allowing for direct electrical coupling of channel material to conductor tiers and simplifying the masking process, thereby enhancing the connectivity and reducing the complexity of stair-step structures in memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional masking processes are used to form stair-step structures, then electrical connections can be established, but the number of masking steps increases and fabrication complexity increases
Solution Approach 1:
The patent extracts and eliminates unnecessary masking steps from the conventional fabrication process. By using self-aligned spacer formation and selective etching, the method removes the need for multiple separate masking operations, thereby reducing fabrication complexity while maintaining reliable electrical connections in the stair-step structures.
Solution Approach 2:
The patent applies preliminary action by forming spacers and conductive layers in a predetermined sequence before final patterning. The spacers are formed first to define the stair-step geometry, followed by selective deposition and etching, which pre-establishes the structural framework and simplifies subsequent connection formation without requiring complex masking.
2Productivity
If vertically-stacked memory cells are formed with traditional methods, then memory arrays can be constructed, but scalability is limited and fabrication efficiency decreases
Solution Approach 1:
The patent transitions from planar to three-dimensional vertically-stacked architecture by forming multiple tiers of memory cells stacked along the vertical dimension. This dimensional change enables higher density and improved scalability while the self-aligned spacer and selective etching methods maintain fabrication efficiency by providing precise structural control without requiring proportionally increased process complexity.
Solution Approach 2:
The patent segments the memory array into multiple vertically-stacked tiers, each with its own conductive layers and channel structures. This segmentation allows independent formation and optimization of each tier, improving scalability and enabling modular fabrication approaches that enhance overall productivity and adaptability.
3Manufacturing precision
If multiple masking steps are used to form different-depth treads, then precise structural control is achieved, but manufacturing complexity and process time increase
Solution Approach 1:
The patent employs self-service mechanisms where previously formed structures serve as self-aligned masks for subsequent etching steps. The spacers automatically define the boundaries of different-depth treads without requiring external masking layers, achieving precise structural control while eliminating the time-consuming masking and de-masking cycles of conventional processes.
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between the substrate and final stair-step formation. These spacers serve as temporary placeholders that automatically define etch boundaries, providing precise structural control during fabrication and then being removed or integrated, thereby reducing overall process time compared to multiple masking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical connectivity and reduces the number of required stair-step structures, leading to more efficient fabrication of vertically-stacked memory cells with improved scalability and performance.
Implementation Method 1
Anisotropically-etched spacers are formed that extend along the first direction directly above the flight of stairs
Data Source
AI summary
A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. An anisotropically-etched spacer is formed extending along the first direction directly above the flight of stairs. The anisotropically-etched spacer is used as a mask while etching through one of the first tiers and one of the second tiers in individual of the stairs to form multiple different-depth treads in the individual stairs along a second direction that is orthogonal to the first direction. Individual of the treads comprise conducting material of individual of the first tiers in the finished-circuitry construction. Other aspects, including structure independent of method, are disclosed.