3D NAND Staircase Beam Structure for RC Delay and Wall Stability
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Solution Overview
Problem
The 3D NAND flash memory faces challenges with increasing RC delay due to rising resistance in connection lines, which affects performance, and the risk of wall structure collapse as the number of stacking layers increases, compromising the integrity of the memory device.
Innovation Solution
A memory device and fabrication method featuring a stack structure with alternating dielectric and electrode layers, including a staircase structure and beam structures that provide mechanical support and electrical connections, reducing resistance and preventing wall structure collapse by separating sub-staircase structures with a first beam structure and using second dielectric layers for mechanical and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacking layers in the memory array structure increases to increase storage capacity, then the storage capacity increases, but the resistance of the connection lines increases causing RC delay problem
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional 3D NAND flash memory with vertically stacked memory cells. This dimensional change allows storage capacity to scale by adding layers in the vertical direction rather than expanding laterally, thereby increasing storage capacity while managing connection line resistance through optimized vertical interconnect structures.
2Reliability
If the staircase structure is disposed between two memory array structures to reduce connection line length and suppress RC delay, then the RC delay problem is suppressed, but the height of the wall structure increases causing collapsing risk
Solution Approach 1:
The patent divides the continuous wall structure into multiple discrete support structures positioned at different heights and locations within the staircase region. This segmentation provides distributed mechanical support to counteract the increased height and reduce collapsing risk, while still maintaining electrical isolation between adjacent memory array structures.
Solution Approach 2:
The patent employs composite material structures combining dielectric materials with different mechanical and electrical properties for the wall structures and support elements. These composite structures provide both the electrical isolation needed for RC delay suppression and the enhanced mechanical strength required to prevent collapsing of taller wall structures.
3Reliability
If electrical connections extend in both directions from the staircase structure to connect memory array structures, then the overall resistance of connection lines decreases, but the wall structure height increases leading to collapse
Solution Approach 1:
The patent segments the wall structure into multiple shorter support elements distributed throughout the staircase region, replacing a single tall continuous wall. This segmentation reduces the effective height of each wall segment, thereby maintaining structural strength while still enabling bidirectional electrical connections with reduced overall resistance.
Data Source
AI summary
A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.