3D NAND Staircase Structure Layout for Precise Contact Isolation
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Solution Overview
Problem
The challenge in microelectronic device fabrication, particularly in 3D NAND memory devices, is the precise and accurate formation of staircase structures and contact features with high aspect ratios, which often leads to misalignments and electrical shorting due to the complexity of reducing feature sizes and increasing density.
Innovation Solution
A method involving a preliminary stack structure with alternating insulative and sacrificial materials, forming stadium structures with opposing staircase structures, and filling trenches with dielectric materials to create a stable and precise microelectronic device architecture, allowing for accurate contact formation and reduced fabrication errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced and density is increased to maximize device integration, then device density and integration level are improved, but fabrication precision and alignment accuracy deteriorate leading to misalignments and electrical shorting
Solution Approach 1:
The fabrication process is segmented into multiple sequential steps: forming preliminary stack structure with alternating insulative and sacrificial materials, creating stadium structures with opposing staircase structures, filling trenches with dielectric materials, and forming contact structures. This segmentation allows each step to be optimized independently, maintaining precision even as overall device density increases
Solution Approach 2:
The patent performs preliminary actions by first forming the preliminary stack structure with alternating materials and creating the stadium structures with staircase features before final contact formation. These preliminary structures serve as templates and guides that ensure precise alignment of subsequent features, preventing misalignment issues that would otherwise occur with reduced feature sizes
2Ease of operation
If contact structures are formed to access conductive structures at staircase steps, then electrical access is improved, but risk of electrical shorting to other tiers increases
Solution Approach 1:
The patent introduces intermediary insulative materials and dielectric materials between the contact structures and adjacent conductive tiers. These intermediary layers act as electrical isolators that prevent shorting while allowing the contact structures to maintain electrical access to their target conductive structures at the staircase steps
Solution Approach 2:
The sacrificial materials are selectively removed to create the staircase structures and contact regions. This extraction process creates precise voids and contact openings that are then filled with appropriate materials, ensuring that contact structures only connect to intended conductive structures while maintaining isolation from other tiers
Data Source
AI summary
A microelectronic device includes a stack structure having blocks separated by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks includes an upper stadium structure, two crest regions, a lower stadium structure, and two bridge regions. The upper stadium structure extends from and between two of the dielectric slot structures, and includes staircase structures having steps including edges of some of the tiers. The two crest regions are horizontally offset from the upper stadium structure. The lower stadium structure is below the upper stadium structure, is interposed between the two crest regions, and includes additional staircase structures. The two bridge regions are interposed between the lower stadium structure and the two of the dielectric slot structures, and extend between the two crest regions. Related memory devices, electronic systems, and methods are also described.