3D NAND Staircase Layout With Dummy Stadium Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional microelectronic device fabrication methods for 3D NAND memory devices result in undesirable defects, diminishing performance, reliability, and durability due to increased feature packing densities and reduced margins for formation errors, leading to structural configurations that are not adequately compact or performance-enhanced.
Innovation Solution
The method involves forming a microelectronic device structure with a preliminary stack structure comprising alternating sacrificial and insulative materials, where stadium structures with staircase configurations are created within a block region, and dummy stadium structures are formed in a non-block region to mitigate edge loading effects and enhance structural integrity, allowing for more efficient packing and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature packing density is increased to maximize device integration, then device density and functionality are improved, but manufacturing precision and reliability deteriorate due to reduced margins for formation errors
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by stacking multiple tiers of memory cells vertically. This dimensional change allows increased device density without proportionally reducing lateral feature dimensions, thereby maintaining manufacturing precision margins while achieving higher integration.
Solution Approach 2:
The patent divides the memory device into multiple discrete tiers or levels, with each tier containing memory cells, charge storage structures, and tunneling structures. This segmentation allows independent formation and control of each tier, reducing the cumulative impact of formation errors and improving overall manufacturing precision despite high density.
2Volume of moving object
If feature dimensions are reduced to increase integration density, then device compactness is improved, but structural integrity and performance deteriorate due to diminished margins for formation errors
Solution Approach 1:
The patent reduces the lateral footprint of the device by stacking memory cells vertically in multiple tiers. This vertical expansion allows the device to maintain compact lateral dimensions while achieving high integration density, and the three-dimensional structure provides additional structural support that enhances reliability despite reduced feature dimensions.
Solution Approach 2:
The patent employs composite structures combining different materials for charge storage (e.g., oxide layers), tunneling (e.g., nitride layers), and conduction. These composite material structures provide enhanced mechanical strength and electrical performance, compensating for the reduced margins associated with smaller feature dimensions and improving overall reliability.
3Ease of manufacture
If conventional fabrication methods are used for high-density structures, then manufacturing simplicity is maintained, but device performance and durability deteriorate due to undesirable defects
Solution Approach 1:
The patent incorporates preliminary protective structures, such as sacrificial layers and support structures, that are formed during the fabrication process to prevent defects during subsequent processing steps. These preliminary actions ensure high reliability without requiring complete redesign of the fabrication methodology, maintaining ease of manufacture while improving device durability.
Solution Approach 2:
The patent converts potentially harmful edge effects and stress concentrations in high-density structures into beneficial features by introducing dummy structures and stress-compensating elements. These elements, which might seem to add complexity, actually improve device reliability by mitigating defects that would otherwise arise from conventional high-density fabrication, while still using standard fabrication processes.
Data Source
AI summary
A microelectronic device includes a stack structure including a block region and a non-block region. The block region includes blocks separated from one another in a first horizontal direction by insulative slot structures and each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks has stadium structures individually including staircase structures having steps comprising edges of some of the tiers. The non-block region neighbors the block region in the first horizontal direction. The non-block region includes additional stadium structures individually terminating at a relatively higher vertical position within the stack structure than at least one of the stadium structures at least partially within boundaries thereof in a second horizontal direction orthogonal to the first horizontal direction. Related memory devices, electronic systems, and methods are also described.