3D NAND Staircase Insulating Film Layout for Etch Defect Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming a staircase structure in semiconductor storage devices with stacked conductive layers is to ensure appropriate electrical access and prevent pattern defects in the conductive layers during manufacturing.
Innovation Solution
The implementation of a staircase structure with insulating films having varying plane widths, including wider insulating films in multi-stage boundary regions to reinforce the structure and prevent erroneous etching, ensuring proper electrical access and reducing pattern defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If insulating films with uniform plane width are used throughout the staircase structure, then manufacturing is simpler, but pattern defects occur in multi-stage boundary regions due to insufficient structural reinforcement
Solution Approach 1:
The patent applies local quality by varying the plane width of insulating films based on their specific location within the staircase structure. In multi-stage boundary regions, insulating films have a first plane width that is wider than the second plane width in other regions. This localized variation provides enhanced structural reinforcement and prevents erroneous etching at critical boundaries while maintaining simpler geometry in non-critical areas, thereby resolving the contradiction between manufacturing simplicity and structural precision.
2Manufacturing precision
If insulating films with varying plane widths are used to reinforce multi-stage boundary regions, then pattern defects are prevented, but manufacturing complexity increases
Solution Approach 1:
The patent employs parameter changes by systematically varying the plane width parameter of insulating films across different regions of the staircase structure. The first plane width in multi-stage boundary regions is specifically designed to be wider than the second plane width in other regions. This controlled parameter variation enhances structural reinforcement and prevents manufacturing defects while following a predictable pattern that can be managed through standardized fabrication processes, thus balancing precision requirements with manufacturing feasibility.
3Reliability
If the staircase structure is formed with precise multi-stage boundaries, then electrical access to conductive layers is improved, but erroneous etching occurs in boundary regions
Solution Approach 1:
The patent implements preliminary anti-action by designing insulating films with a first plane width that is wider than the second plane width in multi-stage boundary regions before the etching process occurs. This preemptive structural reinforcement creates a protective barrier that prevents erroneous etching from occurring during manufacturing, thereby ensuring reliable electrical access to conductive layers without the harmful effects of etching defects.
Data Source
AI summary
A semiconductor storage device of one embodiment includes a stacked body, a first insulating film, and a second insulating film. In the stacked body, conductive layers are stacked with insulating layers in between. The stacked body has a staircase structure. The first insulating film extends through the stacked body in a terrace region in the staircase structure. The second insulating film is in a step part region of the staircase structure. The second insulating film extends through the stacked body in the stacking direction. The second insulating film has a plane width greater than that of the first insulating film. In some examples, a plurality of first and second insulating films may be provided. In such a case, a disposition density of the second insulating films can be greater than that of the first insulating films.