NAND Memory Staircase Hookup Layout for Inter-Area Coupling
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Solution Overview
Problem
Current NAND flash memory devices face challenges in efficiently coupling conductive layers across memory areas, leading to limitations in data storage and retrieval operations due to the lack of an effective bridging mechanism between memory areas.
Innovation Solution
The implementation of a memory device with a bridge portion and hookup portion, featuring a staircase structure with sub-staircases and intermediate portions, which electrically couples conductive layers across memory areas, enhancing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bridge portion is added to couple conductive layers across memory areas, then electrical coupling between memory areas is improved, but device complexity increases
Solution Approach 1:
The bridge portion extends in the first direction (vertical dimension) to connect conductive layers across different memory areas, transforming a planar connection problem into a three-dimensional structure. This allows electrical coupling between memory areas without increasing lateral footprint, resolving the contradiction by adding connectivity in the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The bridge portion is integrated within the existing memory device structure, nesting the coupling function within the overall device architecture. The bridge portion contains conductive layers and insulating layers that are nested within each other, forming a compact structure that provides electrical coupling without significantly increasing external dimensions or overall device complexity.
2Productivity
If a hookup portion with staircase structure is implemented, then data transfer efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The hookup portion is divided into multiple sub-staircases, each comprising several stairs. This segmentation allows the complex staircase structure to be broken down into manageable units, where each sub-staircase can be formed and aligned independently. The segmentation reduces the cumulative precision requirements compared to forming a single large staircase structure, as alignment errors can be contained within individual sub-staircases rather than propagating across the entire structure.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the conductive layers in the staircase structure. These insulating layers provide spacing and electrical isolation, allowing the conductive layers to be positioned at different heights and lateral positions without direct contact. The intermediaries facilitate the staircase geometry by maintaining proper electrical isolation while enabling the stepped configuration that improves data transfer efficiency.
3Reliability
If multiple sub-staircases are arranged in parallel, then electrical coupling robustness is improved, but device area increases
Solution Approach 1:
Multiple sub-staircases are arranged in parallel within the hookup portion, utilizing the lateral dimension to provide redundant electrical coupling paths. By distributing the coupling function across multiple parallel sub-staircases rather than relying on a single connection path, the system achieves improved robustness. The parallel arrangement allows the hookup portion to fit within a compact area by efficiently utilizing available space in the lateral direction.
Data Source
AI summary
According to one embodiment, a memory device includes: first and second memory areas each including conductive layers stacked in a first direction; a hookup portion between first and second memory areas in a second direction, the hookup portion including terraces; and interconnects provided in correspondence with the terraces above the hookup portion. First to fourth sub-staircases of the hookup portion are arranged in order of the first sub-staircase, the second sub-staircase, the third sub-staircase and the fourth sub-staircase in a direction from the first memory area toward the second memory area, and the first to fourth sub-staircases are arranged in order of the first sub-staircase, the second sub-staircase, the fourth sub-staircase and the third sub-staircase in a direction from the interconnects toward the terraces.