3D NAND Staircase Stack Bonding for Dense, Faster Memory
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Solution Overview
Problem
Current memory technologies, such as DRAM, NAND, and MRAM, face limitations in terms of density, speed, and cost, with DRAM being fast but volatile, NAND being dense but slow, and MRAM being neither dense nor fast and expensive.
Innovation Solution
A memory structure featuring a NAND block with a staircase oxide layer structure, vias, and bonding interconnects, which allows for face-to-face bonding with a logic wafer using non-adhesive direct bonding techniques, and a stacked memory device with bitlines and bonding interconnects embedded in a dielectric, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional memory structures (DRAM, NAND, MRAM) are used, then each achieves certain performance characteristics, but they all suffer from significant limitations in density, speed, cost, or volatility
Solution Approach 1:
The memory structure is divided into multiple functional layers including oxide layers, metal layers, and interconnect layers, with each layer performing a specific function. The staircase configuration segments the memory block into multiple levels that can be independently accessed, allowing simultaneous operations on different memory regions to improve overall system reliability and performance
Solution Approach 2:
The patent transitions from planar memory structures to a three-dimensional staircase configuration with multiple levels stacked vertically. This dimensional change increases storage density while maintaining access speed by providing multiple parallel access paths through the stacked levels, thereby balancing density and speed requirements
2Quantity of substance
If NAND memory is used to achieve high density, then storage capacity increases, but access speed deteriorates
Solution Approach 1:
The high-density NAND memory is segmented into multiple smaller memory blocks organized in a staircase configuration. Each block can be independently accessed and operated on, allowing parallel read/write operations across multiple blocks simultaneously. This segmentation maintains high storage density while improving access speed through parallelism
Solution Approach 2:
The memory architecture moves from two-dimensional planar organization to three-dimensional stacked blocks arranged in a staircase pattern. This vertical stacking increases storage density by utilizing the third dimension, while the staggered staircase arrangement provides multiple entry points for data access, maintaining speed by allowing concurrent operations on different levels
3Adaptability or versatility
If complex bonding structures are used to achieve face-to-face bonding, then integration with logic wafer is improved, but manufacturing complexity increases
Solution Approach 1:
The bonding interconnect structure is designed to serve multiple functions: it provides electrical connection between the memory device and logic wafer, serves as a mechanical bonding interface, and acts as a structural support element. This multi-functionality simplifies the overall bonding structure by eliminating the need for separate components for each function, thereby reducing manufacturing complexity while maintaining integration capability
Solution Approach 2:
The bonding interconnect acts as an intermediary element between the memory device and the logic wafer, providing a standardized interface that simplifies the bonding process. The interconnect structure includes alignment features and contact pads that facilitate precise matching and reliable electrical connection, reducing the complexity of direct face-to-face bonding while enabling efficient integration
Data Source
AI summary
A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.