3D NAND Staircase Electrode Voltage Stress Isolation
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Solution Overview
Problem
The existing semiconductor devices face challenges in efficiently connecting multiple electrode layers of three-dimensional memory devices to control circuits, particularly due to voltage stress that can lead to dielectric breakdown and operation errors, such as shorting of electrode layers, which affects the reliability and accuracy of data storage.
Innovation Solution
The semiconductor device incorporates a stacked body with a staircase configuration of electrode layers and insulating layers, supported by columnar portions, where the first and second columnar portions are electrically isolated from each other, and the operating voltage is not applied to the second columnar portions, thereby preventing voltage stress and dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage is applied to connect electrode layers to control circuit, then electrical connection is achieved, but dielectric breakdown occurs causing operation errors
Solution Approach 1:
The device is divided into two distinct stacked portions: a first stacked portion where voltage is applied for electrical connection, and a second stacked portion where voltage is not applied. This segmentation isolates the voltage stress to only the necessary connection path, preventing dielectric breakdown in the data storage region while maintaining electrical connectivity.
Solution Approach 2:
Columnar portions serve as intermediary structures that provide electrical connection between the electrode layers and control circuit without requiring voltage application across the entire stacked body. The columnar portions act as conductive pathways that isolate voltage stress from the data storage electrode layers.
2Productivity
If staircase configuration is used to connect multiple electrode layers, then connection efficiency is improved, but structural complexity increases
Solution Approach 1:
The electrode layers are arranged in a staircase configuration along the stacking direction (vertical dimension), allowing multiple electrode layers to be connected to the control circuit at different heights. This three-dimensional arrangement improves connection efficiency by reducing the number of interconnect layers needed, while the regular staircase pattern maintains manufacturing feasibility.
Data Source
AI summary
According to one embodiment, the insulating layer is provided on the terrace portions. The plurality of contact portions extend through the insulating layer in the stacking direction and contact the terrace portions. The second columnar portion extends through the insulating layer and through the second stacked portion in the stacking direction, and includes a second semiconductor body contacting the first semiconductor region. The first insulating portion divides the first semiconductor region in the first direction. The first insulating portion is provided under a boundary portion between the first stacked portion and the second stacked portion.